RM0444 Rev 5 213/1390
RM0444 Reset and clock control (RCC)
220
5.4.23 RTC domain control register (RCC_BDCR)
Up to three wait states are inserted in case of successive accesses to this register. As this
register is outside of the V
CORE
domain, it is write-protected upon reset. The DBP bit of the
Power control register 1 (PWR_CR1) must be set to allow their modification. Refer to
Section 4.1.2: Battery backup of RTC domain on page 120 for further information.
The register bits are only reset upon RTC domain reset (see Section 5.1.3: RTC domain
reset), except the LSCOSEL, LSCOEN, and BDRST bits that are only reset upon RTC
domain power-on reset. Any internal or external reset has no effect on these bits.
Address offset: 0x5C
Reset value: 0x0000 0000
Bits 9:8 FDCANSEL[1:0]: FDCAN clock source selection
This bitfield is controlled by software to select the FDCAN clock as follows:
00: PCLK
01: PLLQCLK
(1)
10: HSE
11: Reserved
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:2 I2S2SEL[1:0]: I2S2 clock source selection
This bitfield is controlled by software to select I2S2 clock source as follows:
00: SYSCLK
01: PLLPCLK
10: HSI16
11: External I2S clock selected as I2S2
Bits 1:0 I2S1SEL[1:0]: I2S1 clock source selection
This bitfield is controlled by software to select I2S1 clock source as follows:
00: SYSCLK
01: PLLPCLK
10: HSI16
11: External I2S clock selected as I2S1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res.
LSCO
SEL
LSCO
EN
Res. Res. Res. Res. Res. Res. Res. BDRST
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC
EN
Res. Res. Res. Res. Res. RTCSEL[1:0] Res.
LSE
CSSD
LSE
CSSON
LSEDRV[1:0]
LSE
BYP
LSE
RDY
LSEON
rw rw rw r rw rw rw rw r rw
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