Reset and clock control (RCC) RM0444
214/1390 RM0444 Rev 5
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 LSCOSEL: Low-speed clock output selection
Set and cleared by software to select the low-speed output clock:
0: LSI
1: LSE
Bit 24 LSCOEN: Low-speed clock output (LSCO) enable
Set and cleared by software.
0: Disable
1: Enable
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST: RTC domain software reset
Set and cleared by software to reset the RTC domain:
0: No effect
1: Reset
Bit 15 RTCEN: RTC clock enable
Set and cleared by software. The bit enables clock to RTC and TAMP.
0: Disable
1: Enable
Bits 14:10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0]: RTC clock source selection
Set by software to select the clock source for the RTC as follows:
00: No clock
01: LSE
10: LSI
11: HSE divided by 32
Once the RTC clock source is selected, it cannot be changed anymore unless the RTC
domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit
can be used to reset this bitfield to 00.
Bit 7 Reserved, must be kept at reset value.
Bit 6 LSECSSD CSS on LSE failure Detection
Set by hardware to indicate when a failure is detected by the clock security system
on the external 32 kHz oscillator (LSE):
0: No failure detected
1: Failure detected
Bit 5 LSECSSON CSS on LSE enable
Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:
0: Disable
1: Enable
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and
ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.
Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD
=1). In that case the software must disable the LSECSSON bit.
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