RM0444 Rev 5 113/1390
RM0444 Embedded Flash memory (FLASH)
118
3.7.14 FLASH PCROP area B end address register
(FLASH_PCROP1BER)
Address offset: 0x038
Reset value: ‘b0000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word access
3.7.15 FLASH PCROP2 area A start address register
(FLASH_PCROP2ASR)
Address offset: 0x044
Reset value: 0b0000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. PCROP1B_END[8:0]
rw rw rw rw rw rw rw rw rw
Bits 31:9 Reserved, must be kept cleared
Bits 8:0 PCROP1B_END[8:0]: PCROP1B area end offset (Bank 1)
Contains the offset of the last subpage of the PCROP1B area (in Bank 1 for dual-bank
devices)
(1)
.
1. The number of effective bits depends on the size of Flash memory in the device.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. PCROP2A_STRT[8:0]
rw rw rw rw rw rw rw rw rw
Bits 31:9 Reserved, must be kept cleared
Bits 8:0 PCROP2A_STRT[8:0]: PCROP2A area start offset, Bank 2
Contains the offset of the first subpage of the PCROP2A area in Bank 2.
(1)
1. The number of effective bits depends on the size of Flash memory in the device.
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