Reset and clock control (RCC) RM0444
202/1390 RM0444 Rev 5
5.4.17 I/O port in Sleep mode clock enable register (RCC_IOPSMENR)
Address: 0x44
Reset value: 0x0000 003F
Bit 18 TIM17EN: TIM16 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15EN: TIM15 timer clock enable
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 15 TIM14EN: TIM14 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 14 USART1EN: USART1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG, COMP and VREFBUF clock enable
Set and cleared by software.
0: Disable
1: Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
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