ST STM32G0 1 Series - Figure 294. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0

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RM0444 Rev 5 947/1390

RM0444 Inter-integrated circuit (I2C) interface

997

Slave receiver

RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is

set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.

When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an

interrupt is generated.

Figure 294. Transfer sequence flowchart for slave receiver with NOSTRETCH=0

MS19855V2

Slave initialization

Slave reception

Read ADDCODE and DIR in I2C_ISR

Set I2C_ICR.ADDRCF

Write I2C_RXDR.RXDATA

I2C_ISR.ADDR

=1?

Yes

I2C_ISR.RXNE

=1?

Yes

SCL

stretched

Main Page

Table of Contents2
Peripherals Independent Clock Configuration Register2
Documentation Conventions53
General Information53
List of Abbreviations for Registers53
Glossary54
Availability of Peripherals54
Table 1. Peripherals Versus Products54
Memory and Bus Architecture56
System Architecture56
Figure 1. System Architecture56
Memory Organization58
Introduction58
Memory Map and Register Boundary Addresses59
Figure 2. Memory Map59
Table 2. Stm32G0B1Xx and Stm32G0C1Xx Memory Boundary Addresses60
Table 3. Stm32G071Xx and Stm32G081Xx Memory Boundary Addresses60
Table 4. Stm32G051Xx and Stm32G061Xx Memory Boundary Addresses60
Table 5. Stm32G031Xx and Stm32G041Xx Memory Boundary Addresses61
Table 6. Stm32G0X1 Peripheral Register Boundary Addresses62
Embedded SRAM64
Table 7. SRAM Size64
Flash Memory Overview65
Boot Configuration65
Table 8. Boot Modes65
Embedded Flash Memory (FLASH)68
FLASH Introduction68
FLASH Main Features68
FLASH Functional Description69
FLASH Memory Organization69
Table 9. Flash Memory Organization for Single-Bank Devices69
Table 10. Flash Memory Organization for 256 Kbytes Dual-Bank Devices70
FLASH Empty Check71
FLASH Error Code Correction (ECC)71
Table 11. Flash Memory Organization for 512 Kbytes Dual-Bank Devices71
FLASH Read Access Latency72
Table 12. Number of Wait States According to Flash Memory Clock (HCLK) Frequency72
FLASH Memory Acceleration73
FLASH Program and Erase Operations74
FLASH Main Memory Erase Sequences74
Table 13. Page Erase Overview75
Table 14. Mass Erase Overview75
FLASH Main Memory Programming Sequences76
Read-While-Write (RWW) Function79
FLASH Option Bytes80
FLASH Option Byte Description80
Table 15. Option Byte Format80
Table 16. Organization of Option Bytes81
FLASH Option Byte Programming89
FLASH Memory Protection91
FLASH Read Protection (RDP)91
Table 17. Flash Memory Read Protection Status92
FLASH Proprietary Code Readout Protection (PCROP)94
Table 19. Access Status Versus Protection Level and Execution Modes94
Figure 3. Changing Read Protection (RDP) Level94
FLASH Write Protection (WRP)96
Securable Memory Area97
Disabling Core Debug Access98
Forcing Boot from Flash Memory98
FLASH Interrupts98
Table 22. Securable Memory Erase at RDP Level 1 to Level 0 Change98
Figure 4. Example of Disabling Core Debug Access98
Table 23. FLASH Interrupt Requests99
FLASH Registers100
FLASH Access Control Register (FLASH_ACR)100
FLASH Key Register (FLASH_KEYR)101
FLASH Option Key Register (FLASH_OPTKEYR)101
FLASH Status Register (FLASH_SR)102
FLASH Control Register (FLASH_CR)104
FLASH ECC Register (FLASH_ECCR)106
FLASH ECC Register 2 (FLASH_ECCR2)107
FLASH Option Register (FLASH_OPTR)108
Table 10108
FLASH PCROP Area a Start Address Register (FLASH_PCROP1ASR)110
FLASH PCROP Area a End Address Register (FLASH_PCROP1AER)110
FLASH WRP Area a Address Register (FLASH_WRP1AR)111
FLASH WRP Area B Address Register (FLASH_WRP1BR)112
FLASH PCROP Area B Start Address Register (FLASH_PCROP1BSR)112
FLASH PCROP Area B End Address Register (FLASH_PCROP1BER)113
FLASH PCROP2 Area a Start Address Register (FLASH_PCROP2ASR)113
FLASH PCROP2 Area a End Address Register (FLASH_PCROP2AER)114
FLASH WRP2 Area a Address Register (FLASH_WRP2AR)114
FLASH WRP2 Area B Address Register (FLASH_WRP2BR)115
FLASH PCROP2 Area B Start Address Register (FLASH_PCROP2BSR)115
FLASH PCROP2 Area B End Address Register (FLASH_PCROP2BER)116
FLASH Security Register (FLASH_SECR)116
FLASH Register Map117
Table 24. FLASH Register Map and Reset Values117
Power Control (PWR)119
Power Supplies119
ADC and DAC Reference Voltage120
Battery Backup of RTC Domain120
Figure 5. Power Supply Overview120
Voltage Regulator122
Dynamic Voltage Scaling Management123
Power Supply Supervisor124
Power-On Reset (POR) / Power-Down Reset (PDR) / Brown-Out Reset124
(Bor)124
Figure 6. POR, PDR, and BOR Thresholds124
Programmable Voltage Detector (PVD)125
Figure 7. PVD Thresholds125
Low-Power Modes126
Figure 8. Low-Power Modes State Diagram127
Table 25. Low-Power Mode Summary128
Table 26. Functionalities Depending on the Working Mode129
Run Mode131
Low-Power Run Mode (LP Run)131
Low-Power Modes132
Table 27. Low-Power Run132
Sleep Mode133
Table 28. Sleep Mode Summary133
Low-Power Sleep Mode (LP Sleep)134
Stop 0 Mode135
Table 29. Low-Power Sleep Mode Summary135
Table 30. Stop 0 Mode Summary137
Stop 1 Mode138
Table 31. Stop 1 Mode Summary138
Standby Mode139
Table 32. Standby Mode Summary140
Shutdown Mode141
Auto-Wakeup from Low-Power Mode142
Table 33. Shutdown Mode Summary142
PWR Registers143
Power Control Register 1 (PWR_CR1)143
Power Control Register 2 (PWR_CR2)144
Power Control Register 3 (PWR_CR3)146
Power Control Register 4 (PWR_CR4)147
Power Status Register 1 (PWR_SR1)148
Power Status Register 2 (PWR_SR2)149
Power Status Clear Register (PWR_SCR)151
Power Port a Pull-Up Control Register (PWR_PUCRA)151
Power Port a Pull-Down Control Register (PWR_PDCRA)152
Power Port B Pull-Up Control Register (PWR_PUCRB)152
Power Port B Pull-Down Control Register (PWR_PDCRB)153
Power Port C Pull-Up Control Register (PWR_PUCRC)153
Power Port C Pull-Down Control Register (PWR_PDCRC)154
Power Port D Pull-Up Control Register (PWR_PUCRD)154
Power Port D Pull-Down Control Register (PWR_PDCRD)155
Power Port E Pull-Up Control Register (PWR_PUCRE)155
Power Port E Pull-Down Control Register (PWR_PDCRE)156
Power Port F Pull-Up Control Register (PWR_PUCRF)156
Power Port F Pull-Down Control Register (PWR_PDCRF)157
PWR Register Map158
Table 34. PWR Register Map and Reset Values158
Reset and Clock Control (RCC)160
Reset160
Power Reset160
System Reset160
Figure 9. Simplified Diagram of the Reset Circuit161
RTC Domain Reset162
Clocks163
Figure 10. Clock Tree166
HSE Clock167
Figure 11. HSE/ LSE Clock Sources167
HSI16 Clock168
HSI48 Clock169
Pll169
LSE Clock170
LSI Clock170
System Clock (SYSCLK) Selection171
Clock Source Frequency Versus Voltage Scaling171
Clock Security System (CSS)171
Table 35. Clock Source Frequency171
Clock Security System for LSE Clock (LSECSS)172
ADC Clock172
RTC Clock172
Timer Clock173
Watchdog Clock173
Clock-Out Capability173
Internal/External Clock Measurement with TIM14/TIM16/TIM17174
Figure 12. Frequency Measurement with TIM14 in Capture Mode174
Figure 13. Frequency Measurement with TIM16 in Capture Mode175
Figure 14. Frequency Measurement with TIM17 in Capture Mode175
Peripheral Clock Enable Registers176
Low-Power Modes177
RCC Registers178
Clock Control Register (RCC_CR)178
Internal Clock Source Calibration Register (RCC_ICSCR)180
Clock Configuration Register (RCC_CFGR)180
PLL Configuration Register (RCC_PLLCFGR)183
RCC Clock Recovery RC Register (RCC_CRRCR)186
Clock Interrupt Enable Register (RCC_CIER)186
Clock Interrupt Flag Register (RCC_CIFR)187
Clock Interrupt Clear Register (RCC_CICR)189
I/O Port Reset Register (RCC_IOPRSTR)190
AHB Peripheral Reset Register (RCC_AHBRSTR)190
APB Peripheral Reset Register 1 (RCC_APBRSTR1)191
APB Peripheral Reset Register 2 (RCC_APBRSTR2)194
I/O Port Clock Enable Register (RCC_IOPENR)196
AHB Peripheral Clock Enable Register (RCC_AHBENR)197
APB Peripheral Clock Enable Register 1 (RCC_APBENR1)198
APB Peripheral Clock Enable Register 2(RCC_APBENR2)201
I/O Port in Sleep Mode Clock Enable Register (RCC_IOPSMENR)202
AHB Peripheral Clock Enable in Sleep/Stop Mode Register (RCC_AHBSMENR)203
APB Peripheral Clock Enable in Sleep/Stop Mode Register 1205
(Rcc_Apbsmenr1)205
APB Peripheral Clock Enable in Sleep/Stop Mode Register 2208
(Rcc_Apbsmenr2)208
Peripherals Independent Clock Configuration Register (RCC_CCIPR)209
(Rcc_Ccipr2)212
RTC Domain Control Register (RCC_BDCR)213
Control/Status Register (RCC_CSR)215
RCC Register Map217
Table 36. RCC Register Map and Reset Values217
Clock Recovery System (CRS)221
Introduction221
CRS Main Features221
CRS Implementation221
Table 37. CRS Features221
CRS Functional Description222
CRS Block Diagram222
Synchronization Input222
Table 38. CRS Internal Input/Output Signals222
Figure 15. CRS Block Diagram222
Frequency Error Measurement223
Figure 16. CRS Counter Behavior223
Frequency Error Evaluation and Automatic Trimming224
CRS Initialization and Configuration224
CRS Low-Power Modes225
CRS Interrupts225
Table 39. Effect of Low-Power Modes on CRS225
Table 40. Interrupt Control Bits225
CRS Registers226
CRS Control Register (CRS_CR)226
CRS Configuration Register (CRS_CFGR)227
CRS Interrupt and Status Register (CRS_ISR)228
CRS Interrupt Flag Clear Register (CRS_ICR)230
CRS Register Map231
Table 41. CRS Register Map and Reset Values231
General-Purpose I/Os (GPIO)232
Introduction232
GPIO Main Features232
GPIO Functional Description232
Table 42. Port Bit Configuration Table233
Figure 17. Basic Structure of an I/O Port Bit233
General-Purpose I/O (GPIO)234
I/O Pin Alternate Function Multiplexer and Mapping234
I/O Port Control Registers235
I/O Port Data Registers235
I/O Data Bitwise Handling236
GPIO Locking Mechanism236
I/O Alternate Function Input/Output236
External Interrupt/Wakeup Lines237
Input Configuration237
Figure 18. Input Floating/Pull Up/Pull down Configurations237
Output Configuration238
Alternate Function Configuration238
Figure 19. Output Configuration238
Analog Configuration239
Figure 20. Alternate Function Configuration239
Figure 21. High Impedance-Analog Configuration239
Using the HSE or LSE Oscillator Pins as Gpios240
Using the GPIO Pins in the RTC Domain240
USB PD / Dead Battery Support240
GPIO Registers241
GPIO Port Mode Register (Gpiox_Moder)241
(X =A to F)241
GPIO Port Output Type Register (Gpiox_Otyper)241
GPIO Port Output Speed Register (Gpiox_Ospeedr)242
(X = a to F)242
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)242
GPIO Port Input Data Register (Gpiox_Idr)243
(X = a to F)243
GPIO Port Output Data Register (Gpiox_Odr)243
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr)243
GPIO Port Configuration Lock Register (Gpiox_Lckr)244
(X = a to F)244
(X = a to F)245
(X = a to F)246
GPIO Port Bit Reset Register (Gpiox_Brr) (X = a to F)246
GPIO Register Map247
Table 43. GPIO Register Map and Reset Values247
System Configuration Controller (SYSCFG)248
SYSCFG Registers248
SYSCFG Configuration Register 1 (SYSCFG_CFGR1)248
SYSCFG Configuration Register 2 (SYSCFG_CFGR2)251
SYSCFG Interrupt Line 0 Status Register (SYSCFG_ITLINE0)253
SYSCFG Interrupt Line 1 Status Register (SYSCFG_ITLINE1)254
SYSCFG Interrupt Line 2 Status Register (SYSCFG_ITLINE2)254
SYSCFG Interrupt Line 3 Status Register (SYSCFG_ITLINE3)254
SYSCFG Interrupt Line 4 Status Register (SYSCFG_ITLINE4)255
SYSCFG Interrupt Line 5 Status Register (SYSCFG_ITLINE5)256
SYSCFG Interrupt Line 6 Status Register (SYSCFG_ITLINE6)256
SYSCFG Interrupt Line 7 Status Register (SYSCFG_ITLINE7)256
SYSCFG Interrupt Line 8 Status Register (SYSCFG_ITLINE8)257
SYSCFG Interrupt Line 9 Status Register (SYSCFG_ITLINE9)257
SYSCFG Interrupt Line 10 Status Register (SYSCFG_ITLINE10)258
SYSCFG Interrupt Line 11 Status Register (SYSCFG_ITLINE11)258
SYSCFG Interrupt Line 12 Status Register (SYSCFG_ITLINE12)259
SYSCFG Interrupt Line 13 Status Register (SYSCFG_ITLINE13)259
SYSCFG Interrupt Line 14 Status Register (SYSCFG_ITLINE14)260
SYSCFG Interrupt Line 15 Status Register (SYSCFG_ITLINE15)260
SYSCFG Interrupt Line 16 Status Register (SYSCFG_ITLINE16)260
SYSCFG Interrupt Line 17 Status Register (SYSCFG_ITLINE17)261
SYSCFG Interrupt Line 18 Status Register (SYSCFG_ITLINE18)261
SYSCFG Interrupt Line 19 Status Register (SYSCFG_ITLINE19)261
SYSCFG Interrupt Line 20 Status Register (SYSCFG_ITLINE20)262
SYSCFG Interrupt Line 21 Status Register (SYSCFG_ITLINE21)262
SYSCFG Interrupt Line 22 Status Register (SYSCFG_ITLINE22)262
SYSCFG Interrupt Line 23 Status Register (SYSCFG_ITLINE23)263
SYSCFG Interrupt Line 24 Status Register (SYSCFG_ITLINE24)263
SYSCFG Interrupt Line 25 Status Register (SYSCFG_ITLINE25)264
SYSCFG Interrupt Line 26 Status Register (SYSCFG_ITLINE26)264
SYSCFG Interrupt Line 27 Status Register (SYSCFG_ITLINE27)264
SYSCFG Interrupt Line 28 Status Register (SYSCFG_ITLINE28)265
SYSCFG Interrupt Line 29 Status Register (SYSCFG_ITLINE29)265
SYSCFG Interrupt Line 30 Status Register (SYSCFG_ITLINE30)265
SYSCFG Interrupt Line 31 Status Register (SYSCFG_ITLINE31)266
SYSCFG Register Map266
Table 44. SYSCFG Register Map and Reset Values266
Interconnect Matrix270
Introduction270
Connection Summary270
Table 45. Interconnect Matrix270
Interconnection Details271
From TIM1, TIM2, TIM3, TIM4, TIM15, TIM16, and TIM17, to TIM1, TIM2, TIM3, TIM4, and TIM15271
From TIM1, TIM2, TIM3, TIM4, TIM6, TIM15, and EXTI, to ADC272
From ADC to TIM1272
From TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM15, LPTIM1, LPTIM2273
And EXTI, to DAC273
From HSE, LSE, LSI, MCO, MCO2, RTC and TAMP, to TIM2, TIM14273
TIM16, and TIM17273
From RTC, TAMP, COMP1, COMP2, and COMP3 to LPTIM1274
And LPTIM2274
From TIM1, TIM2, TIM3, TIM4, and TIM15, to COMP1, COMP2274
And COMP3274
From Internal Analog Sources to ADC274
From COMP1, COMP2, and COMP3 to TIM1, TIM2, TIM3, TIM4, TIM15275
TIM16, and TIM17275
From System Errors to TIM1, TIM2, TIM3, TIM4, TIM15, TIM16275
And TIM17275
From TIM16, TIM17, USART1, and USART4, to IRTIM276
From TIM14, LPTIM1, and LPTIM2, to DMAMUX276
Direct Memory Access Controller (DMA)277
Introduction277
DMA Main Features277
DMA Implementation278
Dma278
DMA Request Mapping278
DMA Functional Description278
DMA Block Diagram278
Table 46. DMA Implementation278
DMA Pins and Internal Signals279
DMA Transfers279
Table 47. DMA Internal Input/Output Signals279
Figure 22. DMA Block Diagram279
DMA Arbitration280
DMA Channels281
DMA Data Width, Alignment and Endianness284
Table 48. Programmable Data Width and Endian Behavior (When PINC = MINC = 1)285
DMA Error Management286
DMA Interrupts286
DMA Registers286
Table 49. DMA Interrupt Requests286
DMA Interrupt Status Register (DMA_ISR)287
DMA Interrupt Flag Clear Register (DMA289
DMA Channel X Configuration Register (Dma_Ccrx)290
DMA Channel X Number of Data to Transfer Register (Dma_Cndtrx)293
DMA Channel X Peripheral Address Register (Dma_Cparx)294
DMA Channel X Memory Address Register (Dma_Cmarx)294
DMA Register Map295
Table 50. DMA Register Map and Reset Values295
DMA Request Multiplexer (DMAMUX)298
Introduction298
DMAMUX Main Features299
DMAMUX Implementation299
DMAMUX Instantiation299
DMAMUX Mapping299
Table 51. DMAMUX Instantiation299
Table 52. DMAMUX: Assignment of Multiplexer Inputs to Resources300
Table 53. DMAMUX: Assignment of Trigger Inputs to Resources300
Table 54. DMAMUX: Assignment of Synchronization Inputs to Resources301
DMAMUX Functional Description302
DMAMUX Block Diagram302
Figure 23. DMAMUX Block Diagram302
DMAMUX Signals303
DMAMUX Channels303
DMAMUX Request Line Multiplexer303
Table 55. DMAMUX Signals303
Figure 24. Synchronization Mode of the DMAMUX Request Line Multiplexer Channel305
Figure 25. Event Generation of the DMA Request Line Multiplexer Channel305
DMAMUX Request Generator306
DMAMUX Interrupts307
Table 56. DMAMUX Interrupts307
DMAMUX Registers308
DMAMUX Request Line Multiplexer Channel X Configuration Register308
(Dmamux_Cxcr)308
DMAMUX Request Line Multiplexer Interrupt Channel Status Register309
(Dmamux_Csr)309
DMAMUX Request Line Multiplexer Interrupt Clear Flag Register309
(Dmamux_Cfr)309
DMAMUX Request Generator Channel X Configuration Register (Dmamux_Rgxcr)310
DMAMUX Request Generator Interrupt Status Register (DMAMUX_RGSR)311
DMAMUX Request Generator Interrupt Clear Flag Register (DMAMUX_RGCFR)311
DMAMUX Register Map312
Table 57. DMAMUX Register Map and Reset Values312
Nested Vectored Interrupt Controller (NVIC)314
Main Features314
Systick Calibration Value Register314
Interrupt and Exception Vectors314
Table 58. Vector Table314
Extended Interrupt and Event Controller (EXTI)317
EXTI Main Features317
EXTI Block Diagram317
Table 59. EXTI Signal Overview318
Table 60. EVG Pin Overview318
Figure 26. EXTI Block Diagram318
EXTI Connections between Peripherals and CPU319
EXTI Functional Description319
EXTI Configurable Event Input Wakeup320
Table 61. EXTI Event Input Configurations and Register Control320
Figure 27. Configurable Event Trigger Logic CPU Wakeup320
EXTI Direct Event Input Wakeup321
EXTI Mux321
Figure 28. Direct Event Trigger Logic CPU Wakeup321
Table 62. EXTI Line Connections322
Figure 29. EXTI GPIO Mux322
EXTI Functional Behavior323
Table 63. Masking Functionality323
EXTI Registers324
EXTI Rising Trigger Selection Register (EXTI_RTSR1)324
Table 64. EXTI Register Map Sections324
EXTI Falling Trigger Selection Register 1 (EXTI_FTSR1)325
EXTI Software Interrupt Event Register 1 (EXTI_SWIER1)325
EXTI Rising Edge Pending Register 1 (EXTI_RPR1)326
EXTI Falling Edge Pending Register 1 (EXTI_FPR1)327
EXTI Rising Trigger Selection Register 2 (EXTI_RTSR2)328
EXTI Falling Trigger Selection Register 2 (EXTI_FTSR2)328
EXTI Software Interrupt Event Register 2 (EXTI_SWIER2)329
EXTI Rising Edge Pending Register 2 (EXTI_RPR2)329
EXTI Falling Edge Pending Register 2 (EXTI_FPR2)330
EXTI External Interrupt Selection Register (Exti_Exticrx)330
EXTI CPU Wakeup with Interrupt Mask Register (EXTI_IMR1)332
EXTI CPU Wakeup with Event Mask Register (EXTI_EMR1)332
EXTI CPU Wakeup with Interrupt Mask Register (EXTI_IMR2)333
EXTI CPU Wakeup with Event Mask Register (EXTI_EMR2)333
EXTI Register Map334
Table 65. EXTI Controller Register Map and Reset Values334
Cyclic Redundancy Check Calculation Unit (CRC)336
Introduction336
CRC Main Features336
CRC Functional Description337
CRC Block Diagram337
CRC Internal Signals337
CRC Operation337
Table 66. CRC Internal Input/Output Signals337
Figure 30. CRC Calculation Unit Block Diagram337
CRC Registers339
CRC Data Register (CRC_DR)339
CRC Independent Data Register (CRC_IDR)339
CRC Control Register (CRC_CR)340
CRC Initial Value (CRC_INIT)341
CRC Polynomial (CRC_POL)341
CRC Register Map342
Table 67. CRC Register Map and Reset Values342
Analog-To-Digital Converter (ADC)343
Introduction343
ADC Main Features344
ADC Functional Description345
ADC Pins and Internal Signals345
Table 68. ADC Input/Output Pins345
Figure 31. ADC Block Diagram345
ADC Voltage Regulator (ADVREGEN)346
Table 69. ADC Internal Input/Output Signals346
Table 70. External Triggers346
Calibration (ADCAL)347
ADC On-Off Control (ADEN, ADDIS, ADRDY)348
Figure 32. ADC Calibration348
Figure 33. Calibration Factor Forcing348
Figure 34. Enabling/Disabling the ADC349
ADC Clock (CKMODE, PRESC[3:0])350
Figure 35. ADC Clock Scheme350
Table 71. Latency between Trigger and Start of Conversion351
ADC Connectivity352
Figure 36. ADC Connectivity352
Configuring the ADC353
Channel Selection (CHSEL, SCANDIR, CHSELRMOD)353
Programmable Sampling Time (Smpx[2:0])354
Single Conversion Mode (CONT = 0)355
Continuous Conversion Mode (CONT = 1)355
Starting Conversions (ADSTART)356
Timings357
Figure 37. Analog to Digital Conversion Time357
Figure 38. ADC Conversion Timings357
Stopping an Ongoing Conversion (ADSTP)358
Conversion on External Trigger and Trigger Polarity (EXTSEL, EXTEN)358
Table 72. Configuring the Trigger Polarity358
Figure 39. Stopping an Ongoing Conversion358
Discontinuous Mode (DISCEN)359
Programmable Resolution (RES) - Fast Conversion Mode359
End of Conversion, End of Sampling Phase (EOC, EOSMP Flags)360
End of Conversion Sequence (EOS Flag)360
Table 73. Tsar Timings Depending on Resolution360
Example Timing Diagrams361
Hardware/Software Triggers)361
Figure 40. Single Conversions of a Sequence, Software Trigger361
Figure 41. Continuous Conversion of a Sequence, Software Trigger361
Figure 42. Single Conversions of a Sequence, Hardware Trigger362
Figure 43. Continuous Conversions of a Sequence, Hardware Trigger362
Low Frequency Trigger Mode363
Data Management363
Data Register and Data Alignment (ADC_DR, ALIGN)363
ADC Overrun (OVR, OVRMOD)363
Figure 44. Data Alignment and Resolution (Oversampling Disabled: OVSE = 0)363
Figure 45. Example of Overrun (OVR)364
Managing a Sequence of Data Converted Without Using the DMA365
Managing Converted Data Without Using the DMA Without Overrun365
Managing Converted Data Using the DMA365
Low-Power Features366
Wait Mode Conversion366
Auto-Off Mode (AUTOFF)367
Figure 46. Wait Mode Conversion (Continuous Mode, Software Trigger)367
Figure 48. Behavior with WAIT = 1, AUTOFF = 1367
Figure 47. Behavior with WAIT = 0, AUTOFF = 1368
Analog Window Watchdog (AWD1EN, AWD1SGL, AWD1CH, Adc_Awdxcr, Adc_Awdxtr)369
Description of Analog Watchdog 1369
Table 74. Analog Watchdog Comparison369
Figure 49. Analog Watchdog Guarded Area369
Description of Analog Watchdog 2 and 3370
Adc_Awdx_Out Output Signal Generation370
Table 75. Analog Watchdog 1 Channel Selection370
Figure 50. Adc_Awdx_Out Signal Generation371
Figure 51. Adc_Awdx_Out Signal Generation (Awdx Flag Not Cleared by Software)371
Analog Watchdog Threshold Control372
Figure 52. Adc_Awdx_Out Signal Generation (on a Single Channel)372
Figure 53. Analog Watchdog Threshold Update372
Oversampler373
Figure 54. 20-Bit to 16-Bit Result Truncation373
Table 76. Maximum Output Results Vs N and M. Grayed Values Indicates Truncation374
Figure 55. Numerical Example with 5-Bits Shift and Rounding374
ADC Operating Modes Supported When Oversampling375
Analog Watchdog375
Triggered Mode375
Temperature Sensor and Internal Reference Voltage376
Figure 56. Triggered Oversampling Mode (TOVS Bit = 1)376
Figure 57. Temperature Sensor and VREFINT Channel Block Diagram377
Battery Voltage Monitoring378
ADC Interrupts379
Table 77. ADC Interrupts379
Figure 58. VBAT Channel Block Diagram379
ADC Registers381
ADC Interrupt and Status Register (ADC_ISR)381
ADC Interrupt Enable Register (ADC_IER)383
ADC Control Register (ADC_CR)385
ADC Configuration Register 1 (ADC_CFGR1)387
ADC Configuration Register 2 (ADC_CFGR2)391
ADC Sampling Time Register (ADC_SMPR)392
ADC Watchdog Threshold Register (ADC_AWD1TR)393
ADC Watchdog Threshold Register (ADC_AWD2TR)394
ADC Channel Selection Register [Alternate] (ADC_CHSELR)395
ADC Channel Selection Register [Alternate] (ADC_CHSELR)396
ADC Watchdog Threshold Register (ADC_AWD3TR)398
ADC Data Register (ADC_DR)398
ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR)399
ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR)399
ADC Calibration Factor (ADC_CALFACT)400
ADC Common Configuration Register (ADC_CCR)400
ADC Register Map402
Table 78. ADC Register Map and Reset Values402
Digital-To-Analog Converter (DAC)404
Introduction404
DAC Main Features404
Figure 59. Dual-Channel DAC Block Diagram404
DAC Implementation405
Table 79. DAC Features405
DAC Functional Description406
DAC Block Diagram406
DAC Pins and Internal Signals407
Table 80. DAC Input/Output Pins407
Table 81. DAC Internal Input/Output Signals407
DAC Channel Enable408
DAC Data Format408
Table 82. DAC Interconnection408
Figure 60. Data Registers in Single DAC Channel Mode409
Figure 61. Data Registers in Dual DAC Channel Mode409
DAC Conversion410
DAC Output Voltage410
DAC Trigger Selection410
Figure 62. Timing Diagram for Conversion with Trigger Disabled TEN = 0410
DMA Requests411
Noise Generation411
Figure 63. DAC LFSR Register Calculation Algorithm412
Figure 64. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation412
Triangle-Wave Generation413
Figure 65. DAC Triangle Wave Generation413
Figure 66. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation413
DAC Channel Modes414
Table 83. Sample and Refresh Timings415
Table 84. Channel Output Modes Summary416
Figure 67. DAC Sample and Hold Mode Phase Diagram416
DAC Channel Buffer Calibration417
Dual DAC Channel Conversion Modes418
Available)418
DAC Low-Power Modes422
Table 85. Effect of Low-Power Modes on DAC422
DAC Interrupts423
Table 86. DAC Interrupts423
DAC Registers424
DAC Control Register (DAC_CR)424
DAC Software Trigger Register (DAC_SWTRGR)427
DAC Channel1 12-Bit Right-Aligned Data Holding Register (DAC_DHR12R1)428
DAC Channel1 12-Bit Left Aligned Data Holding Register428
(Dac_Dhr12L1)428
DAC Channel1 8-Bit Right Aligned Data Holding Register (DAC_DHR8R1)429
DAC Channel2 12-Bit Right Aligned Data Holding Register (DAC_DHR12R2)429
DAC Channel2 12-Bit Left Aligned Data Holding Register430
(Dac_Dhr12L2)430
DAC Channel2 8-Bit Right-Aligned Data Holding Register (DAC_DHR8R2)430
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)431
Dual DAC 12-Bit Left Aligned Data Holding Register431
(Dac_Dhr12Ld)431
Dual DAC 8-Bit Right Aligned Data Holding Register432
(Dac_Dhr8Rd)432
DAC Channel1 Data Output Register (DAC_DOR1)432
DAC Channel2 Data Output Register (DAC_DOR2)433
DAC Status Register (DAC_SR)433
DAC Calibration Control Register (DAC_CCR)435
DAC Mode Control Register (DAC_MCR)435
DAC Channel1 Sample and Hold Sample Time Register437
(Dac_Shsr1)437
DAC Channel2 Sample and Hold Sample Time Register437
(Dac_Shsr2)437
DAC Sample and Hold Time Register (DAC_SHHR)438
DAC Sample and Hold Refresh Time Register (DAC_SHRR)438
DAC Register Map440
Table 87. DAC Register Map and Reset Values440
Voltage Reference Buffer (VREFBUF)442
Introduction442
VREFBUF Functional Description442
Table 88. VREF Buffer Modes442
VREFBUF Registers443
VREFBUF Control and Status Register (VREFBUF_CSR)443
VREFBUF Calibration Control Register (VREFBUF_CCR)444
VREFBUF Register Map444
Table 89. VREFBUF Register Map and Reset Values444
Comparator (COMP)445
Introduction445
COMP Main Features445
COMP Functional Description446
COMP Block Diagram446
COMP Pins and Internal Signals446
Table 90. COMP1 Non-Inverting Input Assignment446
Figure 68. Comparator Block Diagram446
Table 91. COMP1 Inverting Input Assignment447
Table 92. COMP2 Non-Inverting Input Assignment447
Table 93. COMP2 Inverting Input Assignment447
COMP Reset and Clocks448
Comparator LOCK Mechanism448
Table 94. COMP3 Non-Inverting Input Assignment448
Table 95. COMP3 Inverting Input Assignment448
Window Comparator449
Hysteresis449
Figure 69. Window Mode449
Figure 70. Comparator Hysteresis449
Comparator Output Blanking Function450
COMP Power and Speed Modes450
Figure 71. Comparator Output Blanking450
COMP Low-Power Modes451
COMP Interrupts451
COMP Registers451
Comparator 1 Control and Status Register (COMP1_CSR)451
Table 96. Comparator Behavior in the Low Power Modes451
Table 97. Interrupt Control Bits451
Comparator 2 Control and Status Register (COMP2_CSR)453
Comparator 3 Control and Status Register (COMP3_CSR)455
COMP Register Map458
Table 98. COMP Register Map and Reset Values458
True Random Number Generator (RNG)459
Introduction459
RNG Main Features459
RNG Functional Description460
RNG Block Diagram460
RNG Internal Signals460
Table 99. RNG Internal Input/Output Signals460
Figure 72. RNG Block Diagram460
Random Number Generation461
Figure 73. Entropy Source Model461
RNG Initialization463
RNG Operation464
Figure 74. RNG Initialization Overview464
RNG Clocking465
Error Management465
RNG Low-Power Usage466
RNG Interrupts467
RNG Processing Time467
RNG Entropy Source Validation467
Introduction467
Validation Conditions467
Table 100. RNG Interrupt Requests467
Data Collection468
RNG Registers469
RNG Control Register (RNG_CR)469
RNG Status Register (RNG_SR)470
RNG Data Register (RNG_DR)471
RNG Register Map472
Table 101. RNG Register Map and Reset Map472
AES Hardware Accelerator (AES)473
Introduction473
AES Main Features473
AES Implementation474
AES Functional Description474
AES Block Diagram474
AES Internal Signals474
Table 102. AES Internal Input/Output Signals474
Figure 75. AES Block Diagram474
AES Cryptographic Core475
Figure 76. ECB Encryption and Decryption Principle476
Figure 77. CBC Encryption and Decryption Principle477
Figure 78. CTR Encryption and Decryption Principle478
Figure 79. GCM Encryption and Authentication Principle479
Figure 80. GMAC Authentication Principle479
AES Procedure to Perform a Cipher Operation480
Figure 81. CCM Encryption and Authentication Principle480
AES Decryption Round Key Preparation483
AES Ciphertext Stealing and Data Padding483
AES Task Suspend and Resume484
AES Basic Chaining Modes (ECB, CBC)484
Figure 82. Example of Suspend Mode Management484
Figure 83. ECB Encryption485
Figure 84. ECB Decryption485
Figure 85. CBC Encryption486
Figure 86. CBC Decryption486
Figure 87. ECB/CBC Encryption (Mode 1)487
Figure 88. ECB/CBC Decryption (Mode 3)488
AES Counter (CTR) Mode489
Figure 89. Message Construction in CTR Mode490
Figure 90. CTR Encryption490
Table 103. CTR Mode Initialization Vector Definition491
Figure 91. CTR Decryption491
AES Galois/Counter Mode (GCM)492
Figure 92. Message Construction in GCM492
Table 104. GCM Last Block Definition493
Table 105. GCM Mode IVI Bitfield Initialization494
Figure 93. GCM Authenticated Encryption494
AES Galois Message Authentication Code (GMAC)497
Figure 94. Message Construction in GMAC Mode498
Figure 95. GMAC Authentication Mode498
AES Counter with CBC-MAC (CCM)499
Figure 96. Message Construction in CCM Mode499
Table 106. Initialization of Aes_Ivrx Registers in CCM Mode501
Figure 97. CCM Mode Authenticated Encryption501
AES Data Registers and Data Swapping505
Figure 98. 128-Bit Block Construction with Respect to Data Swap506
AES Key Registers507
AES Initialization Vector Registers507
AES DMA Interface507
Table 107. Key Endianness in Aes_Keyrx Registers (128- or 256-Bit Key Length)507
Figure 99. DMA Transfer of a 128-Bit Data Block During Input Phase508
Figure 100. DMA Transfer of a 128-Bit Data Block During Output Phase508
AES Error Management509
AES Interrupts509
AES Processing Latency510
Table 108. AES Interrupt Requests510
Table 109. Processing Latency for ECB, CBC and CTR510
Table 110. Processing Latency for GCM and CCM (in Clock Cycles)510
AES Registers511
AES Control Register (AES_CR)511
AES Status Register (AES_SR)513
AES Data Input Register (AES_DINR)514
AES Data Output Register (AES_DOUTR)515
AES Key Register 0 (AES_KEYR0)516
AES Key Register 1 (AES_KEYR1)516
AES Key Register 2 (AES_KEYR2)517
AES Key Register 3 (AES_KEYR3)517
AES Initialization Vector Register 0 (AES_IVR0)517
AES Initialization Vector Register 1 (AES_IVR1)518
AES Initialization Vector Register 2 (AES_IVR2)518
AES Initialization Vector Register 3 (AES_IVR3)518
AES Key Register 4 (AES_KEYR4)519
AES Key Register 5 (AES_KEYR5)519
AES Key Register 6 (AES_KEYR6)519
AES Key Register 7 (AES_KEYR7)520
AES Suspend Registers (Aes_Suspxr)520
AES Register Map521
Table 111. AES Register Map and Reset Values521
Advanced-Control Timer (TIM1)523
TIM1 Introduction523
TIM1 Main Features524
Figure 101. Advanced-Control Timer Block Diagram525
TIM1 Functional Description526
Time-Base Unit526
Figure 102. Counter Timing Diagram with Prescaler Division Change from 1 to 2527
Figure 103. Counter Timing Diagram with Prescaler Division Change from 1 to 4527
Counter Modes528
Figure 104. Counter Timing Diagram, Internal Clock Divided by 1529
Figure 105. Counter Timing Diagram, Internal Clock Divided by 2529
Figure 106. Counter Timing Diagram, Internal Clock Divided by 4530
Figure 107. Counter Timing Diagram, Internal Clock Divided by N530
Figure 108. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)531
Figure 109. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)531
Figure 110. Counter Timing Diagram, Internal Clock Divided by 1533
Figure 111. Counter Timing Diagram, Internal Clock Divided by 2533
Figure 112. Counter Timing Diagram, Internal Clock Divided by 4534
Figure 113. Counter Timing Diagram, Internal Clock Divided by N534
Figure 114. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used535
Figure 115. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6536
Figure 116. Counter Timing Diagram, Internal Clock Divided by 2537
Figure 117. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36537
Figure 118. Counter Timing Diagram, Internal Clock Divided by N538
Figure 119. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)538
Repetition Counter539
Figure 120. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)539
Figure 121. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings540
External Trigger Input541
Figure 122. External Trigger Input Block541
Figure 123. TIM1 ETR Input Circuitry541
Clock Selection542
Figure 124. Control Circuit in Normal Mode, Internal Clock Divided by 1542
Figure 125. TI2 External Clock Connection Example543
Figure 126. Control Circuit in External Clock Mode 1544
Figure 127. External Trigger Input Block544
Figure 128. Control Circuit in External Clock Mode 2545
Capture/Compare Channels546
Figure 129. Capture/Compare Channel (Example: Channel 1 Input Stage)546
Figure 130. Capture/Compare Channel 1 Main Circuit546
Figure 131. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch. 2 and 3)547
Figure 132. Output Stage of Capture/Compare Channel (Channel 4)547
Input Capture Mode548
Figure 133. Output Stage of Capture/Compare Channel (Channel 5, Idem Ch. 6)548
PWM Input Mode549
Forced Output Mode550
Figure 134. PWM Input Mode Timing550
Output Compare Mode551
PWM Mode552
Figure 135. Output Compare Mode, Toggle on OC1552
Figure 136. Edge-Aligned PWM Waveforms (ARR=8)553
Figure 137. Center-Aligned PWM Waveforms (ARR=8)554
Asymmetric PWM Mode555
Combined PWM Mode556
Figure 138. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle556
Combined 3-Phase PWM Mode557
Figure 139. Combined PWM Mode on Channel 1 and 3557
Complementary Outputs and Dead-Time Insertion558
Figure 140. 3-Phase Combined PWM Signals with Multiple Trigger Pulses Per Period558
Figure 141. Complementary Output with Dead-Time Insertion559
Figure 142. Dead-Time Waveforms with Delay Greater than the Negative Pulse559
Using the Break Function560
Figure 143. Dead-Time Waveforms with Delay Greater than the Positive Pulse560
Figure 144. Break and Break2 Circuitry Overview562
Figure 145. Various Output Behavior in Response to a Break Event on BRK (OSSI = 1)564
Table 112. Behavior of Timer Outputs Versus BRK/BRK2 Inputs565
Figure 146. PWM Output State Following BRK and BRK2 Pins Assertion (OSSI=1)565
Bidirectional Break Inputs566
Figure 147. PWM Output State Following BRK Assertion (OSSI=0)566
Table 113. Break Protection Disarming Conditions567
Figure 148. Output Redirection (BRK2 Request Not Represented)567
Clearing the Ocxref Signal on an External Event568
Figure 149. Clearing Timx Ocxref568
6-Step PWM Generation569
Figure 150. 6-Step Generation, COM Example (OSSR=1)569
One-Pulse Mode570
Figure 151. Example of One Pulse Mode570
Retriggerable One Pulse Mode571
Encoder Interface Mode572
Figure 152. Retriggerable One Pulse Mode572
Table 114. Counting Direction Versus Encoder Signals573
Figure 153. Example of Counter Operation in Encoder Interface Mode573
UIF Bit Remapping574
Figure 154. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted574
Timer Input XOR Function575
Interfacing with Hall Sensors575
Figure 155. Measuring Time Interval between Edges on 3 Signals575
Figure 156. Example of Hall Sensor Interface577
Timer Synchronization578
Figure 157. Control Circuit in Reset Mode578
Figure 158. Control Circuit in Gated Mode579
Figure 159. Control Circuit in Trigger Mode580
Figure 160. Control Circuit in External Clock Mode 2 + Trigger Mode581
ADC Synchronization582
DMA Burst Mode582
Debug Mode583
TIM1 Registers584
TIM1 Control Register 1 (TIM1_CR1)584
TIM1 Control Register 2 (TIM1_CR2)585
TIM1 Slave Mode Control Register (TIM1_SMCR)588
TIM1 Dma/Interrupt Enable Register (TIM1_DIER)590
Table 115. TIM1 Internal Trigger Connection590
TIM1 Status Register (TIM1_SR)592
TIM1 Event Generation Register (TIM1_EGR)594
TIM1 Capture/Compare Mode Register 1 [Alternate]595
(Tim1_Ccmr1)595
TIM1 Capture/Compare Mode Register 1 [Alternate]596
(Tim1_Ccmr1)596
TIM1 Capture/Compare Mode Register 2 [Alternate]599
(Tim1_Ccmr2)599
TIM1 Capture/Compare Mode Register 2 [Alternate]600
(Tim1_Ccmr2)600
TIM1 Capture/Compare Enable Register602
(Tim1_Ccer)602
Table 116. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature604
TIM1 Counter (TIM1_CNT)605
TIM1 Prescaler (TIM1_PSC)605
TIM1 Auto-Reload Register (TIM1_ARR)605
TIM1 Repetition Counter Register (TIM1_RCR)606
TIM1 Capture/Compare Register 1 (TIM1_CCR1)606
TIM1 Capture/Compare Register 2 (TIM1_CCR2)607
TIM1 Capture/Compare Register 3 (TIM1_CCR3)607
TIM1 Capture/Compare Register 4 (TIM1_CCR4)608
TIM1 Break and Dead-Time Register608
(Tim1_Bdtr)608
TIM1 DMA Control Register (TIM1_DCR)612
TIM1 DMA Address for Full Transfer613
(Tim1_Dmar)613
TIM1 Option Register 1 (TIM1_OR1)614
TIM1 Capture/Compare Mode Register 3614
(Tim1_Ccmr3)614
TIM1 Capture/Compare Register 5 (TIM1_CCR5)615
TIM1 Capture/Compare Register 6 (TIM1_CCR6)616
TIM1 Alternate Function Option Register 1 (TIM1_AF1)617
TIM1 Alternate Function Register 2 (TIM1_AF2)619
TIM1 Timer Input Selection Register (TIM1_TISEL)620
TIM1 Register Map622
Table 117. TIM1 Register Map and Reset Values622
General-Purpose Timers (TIM2/TIM3/TIM4)625
TIM2/TIM3/TIM4 Introduction625
TIM2/TIM3/TIM4 Main Features625
Figure 161. General-Purpose Timer Block Diagram626
TIM2/TIM3/TIM4 Functional Description627
Time-Base Unit627
Figure 162. Counter Timing Diagram with Prescaler Division Change from 1 to 2628
Figure 163. Counter Timing Diagram with Prescaler Division Change from 1 to 4628
Counter Modes629
Figure 164. Counter Timing Diagram, Internal Clock Divided by 1629
Figure 165. Counter Timing Diagram, Internal Clock Divided by 2630
Figure 166. Counter Timing Diagram, Internal Clock Divided by 4630
Figure 167. Counter Timing Diagram, Internal Clock Divided by N631
Figure 168. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)631
Figure 169. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)632
Figure 170. Counter Timing Diagram, Internal Clock Divided by 1633
Figure 171. Counter Timing Diagram, Internal Clock Divided by 2633
Figure 172. Counter Timing Diagram, Internal Clock Divided by 4634
Figure 173. Counter Timing Diagram, Internal Clock Divided by N634
Figure 174. Counter Timing Diagram, Update Event When Repetition Counter635
Figure 175. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6636
Figure 176. Counter Timing Diagram, Internal Clock Divided by 2637
Figure 177. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36637
Figure 178. Counter Timing Diagram, Internal Clock Divided by N638
Figure 179. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)638
Clock Selection639
Figure 180. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)639
Figure 181. Control Circuit in Normal Mode, Internal Clock Divided by 1640
Figure 182. TI2 External Clock Connection Example640
Figure 183. Control Circuit in External Clock Mode 1641
Figure 184. External Trigger Input Block642
Capture/Compare Channels643
Figure 185. Control Circuit in External Clock Mode 2643
Figure 186. Capture/Compare Channel (Example: Channel 1 Input Stage)643
Figure 187. Capture/Compare Channel 1 Main Circuit644
Figure 188. Output Stage of Capture/Compare Channel (Channel 1)644
Input Capture Mode645
PWM Input Mode646
Figure 189. PWM Input Mode Timing646
Forced Output Mode647
Output Compare Mode647
PWM Mode648
Figure 190. Output Compare Mode, Toggle on OC1648
Figure 191. Edge-Aligned PWM Waveforms (ARR=8)649
Figure 192. Center-Aligned PWM Waveforms (ARR=8)651
Asymmetric PWM Mode652
Combined PWM Mode652
Figure 193. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle652
Clearing the Ocxref Signal on an External Event653
Figure 194. Combined PWM Mode on Channels 1 and 3653
Figure 195. Clearing Timx Ocxref654
One-Pulse Mode655
Figure 196. Example of One-Pulse Mode655
22.3.14 Retriggerable One Pulse Mode656
Encoder Interface Mode657
Figure 197. Retriggerable One-Pulse Mode657
Table 118. Counting Direction Versus Encoder Signals658
Figure 198. Example of Counter Operation in Encoder Interface Mode658
UIF Bit Remapping659
Timer Input XOR Function659
Figure 199. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted659
Timers and External Trigger Synchronization660
Figure 200. Control Circuit in Reset Mode660
Figure 201. Control Circuit in Gated Mode661
Figure 202. Control Circuit in Trigger Mode662
Timer Synchronization663
Figure 203. Control Circuit in External Clock Mode 2 + Trigger Mode663
Figure 204. Master/Slave Timer Example663
Figure 205. Master/Slave Connection Example with 1 Channel Only Timers664
Figure 206. Gating TIM2 with OC1REF of TIM3665
Figure 207. Gating TIM2 with Enable of TIM3666
Figure 208. Triggering TIM2 with Update of TIM3666
Figure 209. Triggering TIM2 with Enable of TIM3667
DMA Burst Mode668
Figure 210. Triggering TIM3 and TIM2 with TIM3 TI1 Input668
Debug Mode669
TIM2/TIM3/TIM4 Registers670
Timx Control Register 1 (Timx_Cr1)(X = 2 to 4)670
Timx Control Register 2 (Timx_Cr2)(X = 2 to 4)671
Timx Slave Mode Control Register (Timx_Smcr)(X = 2 to 4)673
Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 2 to 4)676
Table 119. Timx Internal Trigger Connection676
Timx Status Register (Timx_Sr)(X = 2 to 4)677
Timx Event Generation Register (Timx_Egr)(X = 2 to 4)679
Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)680
Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)682
Timx Capture/Compare Mode Register 2 [Alternate] (Timx_Ccmr2)684
Timx Capture/Compare Mode Register 2 [Alternate] (Timx_Ccmr2)685
(Timx_Ccer)(X = 2 to 4)686
Timx Counter [Alternate] (Timx_Cnt)(X = 2 to 4)687
Table 120. Output Control Bit for Standard Ocx Channels687
Timx Counter [Alternate] (Timx_Cnt)(X = 2 to 4)688
Timx Prescaler (Timx_Psc)(X = 2 to 4)688
Timx Auto-Reload Register (Timx_Arr)(X = 2 to 4)689
Timx Capture/Compare Register 1 (Timx_Ccr1)(X = 2 to 4)689
Timx Capture/Compare Register 2 (Timx_Ccr2)(X = 2 to 4)690
Timx Capture/Compare Register 3 (Timx_Ccr3)(X = 2 to 4)690
Timx Capture/Compare Register 4 (Timx_Ccr4)(X = 2 to 4)691
Timx DMA Control Register (Timx_Dcr)(X = 2 to 4)692
Timx DMA Address for Full Transfer (Timx_Dmar)(X = 2 to 4)692
TIM2 Option Register 1 (TIM2_OR1)692
TIM3 Option Register 1 (TIM3_OR1)693
TIM4 Option Register 1 (TIM4_OR1)694
TIM2 Alternate Function Option Register 1 (TIM2_AF1)694
TIM3 Alternate Function Option Register 1 (TIM3_AF1)695
TIM4 Alternate Function Option Register 1 (TIM4_AF1)695
TIM2 Timer Input Selection Register (TIM2_TISEL)696
TIM3 Timer Input Selection Register (TIM3_TISEL)696
TIM4 Timer Input Selection Register (TIM4_TISEL)697
Timx Register Map699
Table 121. TIM2/TIM3/TIM4 Register Map and Reset Values699
Basic Timers (TIM6/TIM7)702
TIM6/TIM7 Introduction702
TIM6/TIM7 Main Features702
Figure 211. Basic Timer Block Diagram702
TIM6/TIM7 Functional Description703
Time-Base Unit703
Figure 212. Counter Timing Diagram with Prescaler Division Change from 1 to 2704
Figure 213. Counter Timing Diagram with Prescaler Division Change from 1 to 4704
Counting Mode705
Figure 214. Counter Timing Diagram, Internal Clock Divided by 1705
Figure 215. Counter Timing Diagram, Internal Clock Divided by 2706
Figure 216. Counter Timing Diagram, Internal Clock Divided by 4706
Figure 217. Counter Timing Diagram, Internal Clock Divided by N707
UIF Bit Remapping708
Clock Source708
Debug Mode709
TIM6/TIM7 Registers709
Timx Control Register 1 (Timx_Cr1)(X = 6 to 7)709
Figure 220. Control Circuit in Normal Mode, Internal Clock Divided by 1709
Timx Control Register 2 (Timx_Cr2)(X = 6 to 7)711
Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 6 to 7)711
Timx Status Register (Timx_Sr)(X = 6 to 7)712
Timx Event Generation Register (Timx_Egr)(X = 6 to 7)712
Timx Counter (Timx_Cnt)(X = 6 to 7)712
Timx Prescaler (Timx_Psc)(X = 6 to 7)713
Timx Auto-Reload Register (Timx_Arr)(X = 6 to 7)713
Timx Register Map714
Table 122. Timx Register Map and Reset Values714
General-Purpose Timers (TIM14)715
TIM14 Introduction715
TIM14 Main Features715
Figure 221. General-Purpose Timer Block Diagram (TIM14)716
TIM14 Functional Description717
Time-Base Unit717
Figure 222. Counter Timing Diagram with Prescaler Division Change from 1 to 2718
Figure 223. Counter Timing Diagram with Prescaler Division Change from 1 to 4718
Counter Modes719
Figure 224. Counter Timing Diagram, Internal Clock Divided by 1719
Figure 225. Counter Timing Diagram, Internal Clock Divided by 2720
Figure 226. Counter Timing Diagram, Internal Clock Divided by 4720
Figure 227. Counter Timing Diagram, Internal Clock Divided by N721
Clock Selection722
Capture/Compare Channels723
Figure 230. Control Circuit in Normal Mode, Internal Clock Divided by 1723
Figure 231. Capture/Compare Channel (Example: Channel 1 Input Stage)723
Input Capture Mode724
Figure 232. Capture/Compare Channel 1 Main Circuit724
Figure 233. Output Stage of Capture/Compare Channel (Channel 1)724
Forced Output Mode725
Output Compare Mode726
PWM Mode727
Figure 234. Output Compare Mode, Toggle on OC1727
One-Pulse Mode728
UIF Bit Remapping728
Figure 235. Edge-Aligned PWM Waveforms (ARR=8)728
Using Timer Output as Trigger for Other Timers (TIM14)729
Debug Mode729
TIM14 Registers730
TIM14 Control Register 1 (TIM14_CR1)730
TIM14 Interrupt Enable Register (TIM14_DIER)731
TIM14 Status Register (TIM14_SR)731
TIM14 Event Generation Register (TIM14_EGR)732
TIM14 Capture/Compare Mode Register 1 [Alternate] (TIM14_CCMR1)733
TIM14 Capture/Compare Enable Register (TIM14_CCER)736
TIM14 Counter (TIM14_CNT)737
Table 123. Output Control Bit for Standard Ocx Channels737
TIM14 Prescaler (TIM14_PSC)738
TIM14 Auto-Reload Register (TIM14_ARR)738
TIM14 Capture/Compare Register 1 (TIM14_CCR1)738
TIM14 Timer Input Selection Register (TIM14_TISEL)739
TIM14 Register Map739
Table 124. TIM14 Register Map and Reset Values739
General-Purpose Timers (TIM15/TIM16/TIM17)741
TIM15/TIM16/TIM17 Introduction741
TIM15 Main Features741
TIM16/TIM17 Main Features742
Figure 236. TIM15 Block Diagram743
Figure 237. TIM16/TIM17 Block Diagram744
TIM15/TIM16/TIM17 Functional Description745
Time-Base Unit745
Figure 238. Counter Timing Diagram with Prescaler Division Change from 1 to 2746
Figure 239. Counter Timing Diagram with Prescaler Division Change from 1 to 4746
Counter Modes747
Figure 240. Counter Timing Diagram, Internal Clock Divided by 1748
Figure 241. Counter Timing Diagram, Internal Clock Divided by 2748
Figure 242. Counter Timing Diagram, Internal Clock Divided by 4749
Figure 243. Counter Timing Diagram, Internal Clock Divided by N749
Repetition Counter751
Clock Selection752
Figure 246. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings752
Figure 247. Control Circuit in Normal Mode, Internal Clock Divided by 1753
Figure 248. TI2 External Clock Connection Example753
Capture/Compare Channels754
Figure 249. Control Circuit in External Clock Mode 1754
Figure 250. Capture/Compare Channel (Example: Channel 1 Input Stage)755
Figure 251. Capture/Compare Channel 1 Main Circuit755
Input Capture Mode756
Figure 252. Output Stage of Capture/Compare Channel (Channel 1)756
Figure 253. Output Stage of Capture/Compare Channel (Channel 2 for TIM15)756
PWM Input Mode (Only for TIM15)757
Forced Output Mode758
Figure 254. PWM Input Mode Timing758
Output Compare Mode759
PWM Mode760
Figure 255. Output Compare Mode, Toggle on OC1760
Combined PWM Mode (TIM15 Only)761
Figure 256. Edge-Aligned PWM Waveforms (ARR=8)761
Complementary Outputs and Dead-Time Insertion762
Figure 257. Combined PWM Mode on Channel 1 and 2762
Figure 258. Complementary Output with Dead-Time Insertion763
Figure 259. Dead-Time Waveforms with Delay Greater than the Negative Pulse763
Using the Break Function764
Figure 260. Dead-Time Waveforms with Delay Greater than the Positive Pulse764
Figure 261. Break Circuitry Overview766
Figure 262. Output Behavior in Response to a Break768
Bidirectional Break Inputs769
Table 125. Break Protection Disarming Conditions769
Figure 263. Output Redirection770
One-Pulse Mode771
Figure 264. Example of One Pulse Mode772
Retriggerable One Pulse Mode (TIM15 Only)773
UIF Bit Remapping773
Figure 265. Retriggerable One Pulse Mode773
Timer Input XOR Function (TIM15 Only)775
Figure 266. Measuring Time Interval between Edges on 2 Signals775
External Trigger Synchronization (TIM15 Only)776
Figure 267. Control Circuit in Reset Mode776
Figure 268. Control Circuit in Gated Mode777
Slave Mode - Combined Reset + Trigger Mode778
DMA Burst Mode778
Figure 269. Control Circuit in Trigger Mode778
Timer Synchronization (TIM15)780
Using Timer Output as Trigger for Other Timers (TIM16/TIM17)780
Debug Mode780
TIM15 Registers781
TIM15 Control Register 1 (TIM15_CR1)781
TIM15 Control Register 2 (TIM15_CR2)782
TIM15 Slave Mode Control Register (TIM15_SMCR)784
TIM15 Dma/Interrupt Enable Register (TIM15_DIER)785
Table 126. Timx Internal Trigger Connection785
TIM15 Status Register (TIM15_SR)786
TIM15 Event Generation Register (TIM15_EGR)788
TIM15 Capture/Compare Mode Register 1 [Alternate]789
(Tim15_Ccmr1)789
(Tim15_Ccmr1)790
TIM15 Capture/Compare Enable Register (TIM15_CCER)793
Table 127. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature795
TIM15 Counter (TIM15_CNT)796
TIM15 Prescaler (TIM15_PSC)796
TIM15 Auto-Reload Register (TIM15_ARR)796
TIM15 Repetition Counter Register (TIM15_RCR)797
TIM15 Capture/Compare Register 1 (TIM15_CCR1)797
TIM15 Capture/Compare Register 2 (TIM15_CCR2)798
TIM15 Break and Dead-Time Register (TIM15_BDTR)798
TIM15 DMA Control Register (TIM15_DCR)801
TIM15 DMA Address for Full Transfer (TIM15_DMAR)801
TIM15 Alternate Register 1 (TIM15_AF1)802
TIM15 Input Selection Register (TIM15_TISEL)803
TIM15 Register Map804
Table 128. TIM15 Register Map and Reset Values804
TIM16/TIM17 Registers807
Timx Control Register 1 (Timx_Cr1)(X = 16 to 17)807
Timx Control Register 2 (Timx_Cr2)(X = 16 to 17)808
Timx Dma/Interrupt Enable Register (Timx_Dier)(X = 16 to 17)809
Timx Status Register (Timx_Sr)(X = 16 to 17)810
Timx Event Generation Register (Timx_Egr)(X = 16 to 17)811
Timx Capture/Compare Mode Register 1 [Alternate] (Timx_Ccmr1)812
Timx Capture/Compare Enable Register (Timx_Ccer)(X = 16 to 17)815
Timx Counter (Timx_Cnt)(X = 16 to 17)817
Table 129. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature817
Timx Prescaler (Timx_Psc)(X = 16 to 17)818
Timx Auto-Reload Register (Timx_Arr)(X = 16 to 17)818
Timx Repetition Counter Register (Timx_Rcr)(X = 16 to 17)819
Timx Capture/Compare Register 1 (Timx_Ccr1)(X = 16 to 17)819
Timx Break and Dead-Time Register (Timx_Bdtr)(X = 16 to 17)820
Timx DMA Control Register (Timx_Dcr)(X = 16 to 17)823
Timx DMA Address for Full Transfer (Timx_Dmar)(X = 16 to 17)823
TIM16 Alternate Function Register 1 (TIM16_AF1)824
TIM16 Input Selection Register (TIM16_TISEL)825
TIM17 Alternate Function Register 1 (TIM17_AF1)826
TIM17 Input Selection Register (TIM17_TISEL)827
TIM16/TIM17 Register Map829
Table 130. TIM16/TIM17 Register Map and Reset Values829
Low-Power Timer (LPTIM)831
Introduction831
LPTIM Main Features831
LPTIM Implementation832
LPTIM Functional Description832
LPTIM Block Diagram832
Table 131. Stm32G0X1 LPTIM Features832
Figure 270. Low-Power Timer Block Diagram (LPTIM1 and LPTIM2832
LPTIM Pins and Internal Signals833
LPTIM Input and Trigger Mapping833
Table 132. LPTIM Input/Output Pins833
Table 133. LPTIM Internal Signals833
Table 134. LPTIM1 External Trigger Connection833
Table 135. LPTIM2 External Trigger Connection834
Table 136. LPTIM1 Input 1 Connection834
Table 137. LPTIM1 Input 2 Connection834
Table 138. LPTIM2 Input 1 Connection834
LPTIM Reset and Clocks835
Glitch Filter835
Prescaler836
Trigger Multiplexer836
Table 139. Prescaler Division Ratios836
Figure 271. Glitch Filter Timing Diagram836
Operating Mode837
Figure 272. LPTIM Output Waveform, Single Counting Mode Configuration837
Figure 273. LPTIM Output Waveform, Single Counting Mode Configuration838
Figure 274. LPTIM Output Waveform, Continuous Counting Mode Configuration838
Timeout Function839
Waveform Generation839
Register Update840
Figure 275. Waveform Generation840
Counter Mode841
Timer Enable841
Timer Counter Reset842
Encoder Mode842
Table 140. Encoder Counting Scenarios843
Debug Mode844
LPTIM Low-Power Modes844
Table 141. Effect of Low-Power Modes on the LPTIM844
Figure 276. Encoder Mode Counting Sequence844
LPTIM Interrupts845
LPTIM Registers845
Table 142. Interrupt Events845
LPTIM Interrupt and Status Register (LPTIM_ISR)846
LPTIM Interrupt Clear Register (LPTIM_ICR)847
LPTIM Interrupt Enable Register (LPTIM_IER)847
LPTIM Configuration Register (LPTIM_CFGR)848
LPTIM Control Register (LPTIM_CR)851
LPTIM Compare Register (LPTIM_CMP)852
LPTIM Autoreload Register (LPTIM_ARR)853
LPTIM Counter Register (LPTIM_CNT)853
LPTIM Configuration Register 2 (LPTIM_CFGR2)854
LPTIM Register Map855
Table 143. LPTIM Register Map and Reset Values855
Infrared Interface (IRTIM)857
Figure 277. IRTIM Internal Hardware Connections857
Independent Watchdog (IWDG)858
Introduction858
IWDG Main Features858
IWDG Functional Description858
IWDG Block Diagram858
Figure 278. Independent Watchdog Block Diagram858
Window Option859
Hardware Watchdog860
Register Access Protection860
Debug Mode860
IWDG Registers861
IWDG Key Register (IWDG_KR)861
IWDG Prescaler Register (IWDG_PR)862
IWDG Reload Register (IWDG_RLR)863
IWDG Status Register (IWDG_SR)864
IWDG Window Register (IWDG_WINR)865
IWDG Register Map866
Table 144. IWDG Register Map and Reset Values866
System Window Watchdog (WWDG)867
Introduction867
WWDG Main Features867
WWDG Functional Description867
WWDG Block Diagram868
Enabling the Watchdog868
Controlling the Down-Counter868
How to Program the Watchdog Timeout868
Figure 279. Watchdog Block Diagram868
Figure 280. Window Watchdog Timing Diagram869
Debug Mode870
WWDG Interrupts870
WWDG Registers870
WWDG Control Register (WWDG_CR)870
WWDG Configuration Register (WWDG_CFR)871
WWDG Status Register (WWDG_SR)872
WWDG Register Map872
Table 145. WWDG Register Map and Reset Values872
Real-Time Clock (RTC)873
Introduction873
RTC Main Features873
RTC Functional Description874
RTC Block Diagram874
Figure 281. RTC Block Diagram874
RTC Pins and Internal Signals875
Table 146. RTC Input/Output Pins875
Table 147. RTC Internal Input/Output Signals875
Gpios Controlled by the RTC and TAMP876
Table 148. RTC Interconnection876
Table 149. PC13 Configuration876
Clock and Prescalers878
Table 150. RTC_OUT Mapping878
Real-Time Clock and Calendar879
Programmable Alarms880
Periodic Auto-Wakeup880
RTC Initialization and Configuration881
Reading the Calendar883
Resetting the RTC884
RTC Synchronization884
RTC Reference Clock Detection885
RTC Smooth Digital Calibration885
Timestamp Function887
Calibration Clock Output888
Tamper and Alarm Output888
RTC Low-Power Modes889
Table 151. Effect of Low-Power Modes on RTC889
Table 152. RTC Pins Functionality over Modes889
RTC Interrupts890
RTC Registers890
RTC Time Register (RTC_TR)890
Table 153. Interrupt Requests890
RTC Date Register (RTC_DR)891
RTC Sub Second Register (RTC_SSR)892
RTC Initialization Control and Status Register (RTC_ICSR)892
RTC Prescaler Register (RTC_PRER)894
RTC Wakeup Timer Register (RTC_WUTR)895
RTC Control Register (RTC_CR)895
RTC Write Protection Register (RTC_WPR)898
RTC Calibration Register (RTC_CALR)899
RTC Shift Control Register (RTC_SHIFTR)900
RTC Timestamp Time Register (RTC_TSTR)901
RTC Timestamp Date Register (RTC_TSDR)901
RTC Timestamp Sub Second Register (RTC_TSSSR)902
RTC Alarm a Register (RTC_ALRMAR)903
RTC Alarm a Sub Second Register (RTC_ALRMASSR)904
RTC Alarm B Register (RTC_ALRMBR)905
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)906
RTC Status Register (RTC_SR)906
RTC Masked Interrupt Status Register (RTC_MISR)907
RTC Status Clear Register (RTC_SCR)908
RTC Register Map910
Table 154. RTC Register Map and Reset Values910
Tamper and Backup Registers (TAMP)912
Introduction912
TAMP Main Features912
TAMP Functional Description913
TAMP Block Diagram913
Figure 282. TAMP Block Diagram913
TAMP Pins and Internal Signals914
TAMP Register Write Protection914
Table 155. TAMP Input/Output Pins914
Table 156. TAMP Internal Input/Output Signals914
Table 157. TAMP Interconnection914
Tamper Detection915
TAMP Low-Power Modes917
TAMP Interrupts917
TAMP Registers917
Table 158. Effect of Low-Power Modes on TAMP917
Table 159. Interrupt Requests917
TAMP Control Register 1 (TAMP_CR1)918
TAMP Control Register 2 (TAMP_CR2)919
TAMP Filter Control Register (TAMP_FLTCR)920
TAMP Interrupt Enable Register (TAMP_IER)921
TAMP Status Register (TAMP_SR)922
TAMP Masked Interrupt Status Register (TAMP_MISR)923
TAMP Status Clear Register (TAMP_SCR)924
TAMP Backup X Register (Tamp_Bkpxr)925
TAMP Register Map926
Table 160. TAMP Register Map and Reset Values926
Inter-Integrated Circuit (I2C) Interface927
Introduction927
I2C Main Features927
I2C Implementation928
I2C Functional Description928
Table 161. Stm32G0X1 I2C Implementation928
I2C1 Block Diagram929
Figure 283. I2C1 Block Diagram929
I2C2 Block Diagram930
Figure 284. I2C2 Block Diagram930
I2C Pins and Internal Signals931
I2C Clock Requirements931
Mode Selection931
Table 162. I2C Input/Output Pins931
Table 163. I2C Internal Input/Output Signals931
I2C Initialization932
Figure 285. I2C Bus Protocol932
Table 164. Comparison of Analog Vs. Digital Filters933
Figure 286. Setup and Hold Timings934
Table 165. I2C-Smbus Specification Data Setup and Hold Times935
Software Reset937
Figure 287. I2C Initialization Flowchart937
Data Transfer938
Figure 288. Data Reception938
Figure 289. Data Transmission939
I2C Slave Mode940
Table 166. I2C Configuration940
Figure 290. Slave Initialization Flowchart942
Figure 291. Transfer Sequence Flowchart for I2C Slave Transmitter944
Figure 292. Transfer Sequence Flowchart for I2C Slave Transmitter945
Figure 293. Transfer Bus Diagrams for I2C Slave Transmitter946
Figure 294. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0947
Figure 295. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1948
Figure 296. Transfer Bus Diagrams for I2C Slave Receiver948
I2C Master Mode949
Figure 297. Master Clock Generation950
Table 167. I2C-Smbus Specification Clock Timings951
Figure 298. Master Initialization Flowchart952
Figure 299. 10-Bit Address Read Access with HEAD10R=0952
Figure 300. 10-Bit Address Read Access with HEAD10R=1953
Figure 301. Transfer Sequence Flowchart for I2C Master Transmitter for N≤255 Bytes954
Figure 302. Transfer Sequence Flowchart for I2C Master Transmitter for N>255 Bytes955
Figure 303. Transfer Bus Diagrams for I2C Master Transmitter956
Figure 304. Transfer Sequence Flowchart for I2C Master Receiver for N≤255 Bytes958
Figure 305. Transfer Sequence Flowchart for I2C Master Receiver for N >255 Bytes959
Figure 306. Transfer Bus Diagrams for I2C Master Receiver960
I2C_TIMINGR Register Configuration Examples961
Table 168. Examples of Timing Settings for Fi2Cclk = 8 Mhz961
Table 169. Examples of Timings Settings for Fi2Cclk = 16 Mhz961
Smbus Specific Features962
Table 170. Examples of Timings Settings for Fi2Cclk = 48 Mhz962
Table 171. Smbus Timeout Specifications964
Smbus Initialization965
Figure 307. Timeout Intervals for T965
Table 172. Smbus with PEC Configuration966
Table 173. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies966
Smbus: I2C_TIMEOUTR Register Configuration Examples967
Table 174. Examples of TIMEOUTB Settings for Various I2CCLK Frequencies967
Smbus Slave Mode968
Table 175. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies (Max T IDLE = 50 Μs)968
Figure 308. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC969
Figure 309. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)969
Figure 310. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC971
Figure 311. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)972
Figure 312. Bus Transfer Diagrams for Smbus Master Transmitter973
Figure 313. Bus Transfer Diagrams for Smbus Master Receiver975
Wakeup from Stop Mode on Address Match976
Error Conditions976
DMA Requests978
Debug Mode979
I2C Low-Power Modes979
Table 176. Effect of Low-Power Modes on the I2C979
I2C Interrupts980
Table 177. I2C Interrupt Requests980
I2C Registers981
I2C Control Register 1 (I2C_CR1)981
I2C Control Register 2 (I2C_CR2)984
I2C Own Address 1 Register (I2C_OAR1)987
I2C Own Address 2 Register (I2C_OAR2)988
I2C Timing Register (I2C_TIMINGR)989
I2C Timeout Register (I2C_TIMEOUTR)990
I2C Interrupt and Status Register (I2C_ISR)991
I2C Interrupt Clear Register (I2C_ICR)993
I2C PEC Register (I2C_PECR)994
I2C Receive Data Register (I2C_RXDR)995
I2C Transmit Data Register (I2C_TXDR)995
I2C Register Map996
Table 178. I2C Register Map and Reset Values996
Universal Synchonous Receiver Transmitter (USART)998
USART Introduction998
USART Main Features999
USART Extended Features1000
USART Implementation1000
Table 179. Stm32G0X1 Features1000
Table 180. USART / LPUART Features1001
USART Functional Description1002
USART Block Diagram1002
Figure 314. USART Block Diagram1002
USART Signals1003
USART Character Description1004
Figure 315. Word Length Programming1005
USART Fifos and Thresholds1006
USART Transmitter1006
Figure 316. Configurable Stop Bits1007
USART Receiver1010
Figure 317. TC/TXE Behavior When Transmitting1010
Figure 318. Start Bit Detection When Oversampling by 16 or 81011
Figure 319. Usart_Ker_Ck Clock Divider Block Diagram1014
Figure 320. Data Sampling When Oversampling by 161015
Table 181. Noise Detection from Sampled Data1016
Figure 321. Data Sampling When Oversampling by 81016
USART Baud Rate Generation1017
Tolerance of the USART Receiver to Clock Deviation1018
Table 182. Tolerance of the USART Receiver When BRR [3:0] = 00001019
USART Auto Baud Rate Detection1020
Table 183. Tolerance of the USART Receiver When BRR[3:0] Is Different from 00001020
USART Multiprocessor Communication1022
Figure 322. Mute Mode Using Idle Line Detection1023
USART Modbus Communication1024
Figure 323. Mute Mode Using Address Mark Detection1024
USART Parity Control1025
Table 184. USART Frame Formats1025
USART LIN (Local Interconnection Network) Mode1026
Figure 324. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)1027
USART Synchronous Mode1028
Figure 325. Break Detection in LIN Mode Vs. Framing Error Detection1028
Figure 326. USART Example of Synchronous Master Transmission1029
Figure 327. USART Data Clock Timing Diagram in Synchronous Master Mode1029
Figure 328. USART Data Clock Timing Diagram in Synchronous Master Mode1030
Figure 329. USART Data Clock Timing Diagram in Synchronous Slave Mode1031
USART Single-Wire Half-Duplex Communication1032
USART Receiver Timeout1032
USART Smartcard Mode1033
Figure 330. ISO 7816-3 Asynchronous Protocol1033
Figure 331. Parity Error Detection Using the 1.5 Stop Bits1035
USART Irda SIR ENDEC Block1037
Figure 332. Irda SIR ENDEC Block Diagram1039
Figure 333. Irda Data Modulation (3/16) - Normal Mode1039
Continuous Communication Using USART and DMA1040
Figure 334. Transmission Using DMA1041
RS232 Hardware Flow Control and RS485 Driver Enable1042
Figure 335. Reception Using DMA1042
Figure 336. Hardware Flow Control between 2 Usarts1042
Figure 337. RS232 RTS Flow Control1043
Figure 338. RS232 CTS Flow Control1044
USART Low-Power Management1045
Figure 339. Wakeup Event Verified (Wakeup Event = Address Match, FIFO Disabled)1047
Figure 340. Wakeup Event Not Verified1047
USART in Low-Power Modes1048
Table 185. Effect of Low-Power Modes on the USART1048
USART Interrupts1049
Table 186. USART Interrupt Requests1049
USART Registers1050
USART Control Register 1 [Alternate] (USART_CR1)1050
USART Control Register 1 [Alternate] (USART_CR1)1054
USART Control Register 2 (USART_CR2)1057
USART Control Register 3 (USART_CR3)1061
USART Baud Rate Register (USART_BRR)1066
USART Guard Time and Prescaler Register (USART_GTPR)1066
USART Receiver Timeout Register (USART_RTOR)1067
USART Request Register (USART_RQR)1068
USART Interrupt and Status Register [Alternate] (USART_ISR)1069
USART Interrupt and Status Register [Alternate] (USART_ISR)1075
USART Interrupt Flag Clear Register (USART_ICR)1080
USART Receive Data Register (USART_RDR)1082
USART Transmit Data Register (USART_TDR)1082
USART Prescaler Register (USART_PRESC)1083
USART Register Map1084
Table 187. USART Register Map and Reset Values1084
Low-Power Universal Asynchronous Receiver1086
Transmitter (LPUART)1086
LPUART Introduction1086
LPUART Main Features1087
LPUART Implementation1088
Table 188. Stm32G0X1 Features1088
Table 189. USART / LPUART Features1088
LPUART Functional Description1089
LPUART Block Diagram1089
Figure 341. LPUART Block Diagram1089
LPUART Signals1090
LPUART Character Description1090
LPUART Fifos and Thresholds1091
Figure 342. LPUART Word Length Programming1091
LPUART Transmitter1092
Figure 343. Configurable Stop Bits1093
Figure 344. TC/TXE Behavior When Transmitting1094
LPUART Receiver1095
Figure 345. Lpuart_Ker_Ck Clock Divider Block Diagram1098
LPUART Baud Rate Generation1099
Table 190. Error Calculation for Programmed Baud Rates at Lpuart_Ker_Ck_Pres = 32,768 Khz1099
Tolerance of the LPUART Receiver to Clock Deviation1100
Table 191. Error Calculation for Programmed Baud Rates at Fck = 100 Mhz1100
LPUART Multiprocessor Communication1101
Table 192. Tolerance of the LPUART Receiver1101
Figure 346. Mute Mode Using Idle Line Detection1102
LPUART Parity Control1103
Figure 347. Mute Mode Using Address Mark Detection1103
LPUART Single-Wire Half-Duplex Communication1104
Continuous Communication Using DMA and LPUART1104
Figure 348. Transmission Using DMA1105
Figure 349. Reception Using DMA1106
RS232 Hardware Flow Control and RS485 Driver Enable1107
Figure 350. Hardware Flow Control between 2 Lpuarts1107
Figure 351. RS232 RTS Flow Control1107
Figure 352. RS232 CTS Flow Control1108
LPUART Low-Power Management1109
Figure 353. Wakeup Event Verified1111
Figure 354. Wakeup Event Not Verified1111
LPUART in Low-Power Modes1112
Table 194. Effect of Low-Power Modes on the LPUART1112
LPUART Interrupts1113
Table 195. LPUART Interrupt Requests1113
LPUART Registers1114
LPUART Control Register 1 [Alternate] (LPUART_CR1)1114
LPUART Control Register 1 [Alternate] (LPUART_CR1)1117
LPUART Control Register 2 (LPUART_CR2)1120
LPUART Control Register 3 (LPUART_CR3)1122
LPUART Baud Rate Register (LPUART_BRR)1125
LPUART Request Register (LPUART_RQR)1126
LPUART Interrupt and Status Register [Alternate] (LPUART_ISR)1126
LPUART Interrupt and Status Register [Alternate] (LPUART_ISR)1131
LPUART Interrupt Flag Clear Register (LPUART_ICR)1134
LPUART Receive Data Register (LPUART_RDR)1135
LPUART Transmit Data Register (LPUART_TDR)1135
LPUART Prescaler Register (LPUART_PRESC)1136
LPUART Register Map1137
Table 196. LPUART Register Map and Reset Values1137
Serial Peripheral Interface / Integrated Interchip Sound (SPI/I2S)1139
Introduction1139
SPI Main Features1139
I2S Main Features1140
SPI/I2S Implementation1140
Table 197. Stm32G0X1 SPI and SPI/I2S Implementation1140
SPI Functional Description1141
General Description1141
Figure 355. SPI Block Diagram1141
Communications between One Master and One Slave1142
Figure 356. Full-Duplex Single Master/ Single Slave Application1142
Figure 357. Half-Duplex Single Master/ Single Slave Application1143
Standard Multi-Slave Communication1144
Figure 358. Simplex Single Master/Single Slave Application1144
Multi-Master Communication1145
Figure 359. Master and Three Independent Slaves1145
Slave Select (NSS) Pin Management1146
Figure 360. Multi-Master Application1146
Communication Formats1147
Figure 361. Hardware/Software Slave Select Management1147
Figure 362. Data Clock Timing Diagram1148
Configuration of SPI1149
Figure 363. Data Alignment When Data Length Is Not Equal to 8-Bit or 16-Bit1149
Procedure for Enabling SPI1150
Data Transmission and Reception Procedures1150
Figure 364. Packing Data in FIFO for Transmission and Reception1153
Figure 365. Master Full-Duplex Communication1156
Figure 366. Slave Full-Duplex Communication1157
Figure 367. Master Full-Duplex Communication with CRC1158
Figure 368. Master Full-Duplex Communication in Packed Mode1159
SPI Status Flags1160
SPI Error Flags1161
NSS Pulse Mode1162
TI Mode1162
Figure 369. NSSP Pulse Generation in Motorola SPI Master Mode1162
CRC Calculation1163
Figure 370. TI Mode Transfer1163
SPI Interrupts1165
Table 198. SPI Interrupt Requests1165
I2S Functional Description1166
I2S General Description1166
Figure 371. I2S Block Diagram1166
Supported Audio Protocols1167
Figure 372. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy)1168
Figure 373. I 2 S Philips Standard Waveforms (24-Bit Frame)1168
Figure 374. Transmitting 0X8Eaa331169
Figure 375. Receiving 0X8Eaa331169
Figure 376. I1169
Figure 377. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame1169
Figure 378. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length1170
Figure 379. MSB Justified 24-Bit Frame Length1170
Figure 380. MSB Justified 16-Bit Extended to 32-Bit Packet Frame1171
Figure 381. LSB Justified 16-Bit or 32-Bit Full-Accuracy1171
Figure 382. LSB Justified 24-Bit Frame Length1171
Figure 383. Operations Required to Transmit 0X3478Ae1172
Figure 384. Operations Required to Receive 0X3478Ae1172
Figure 385. LSB Justified 16-Bit Extended to 32-Bit Packet Frame1172
Figure 386. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame1173
Figure 387. PCM Standard Waveforms (16-Bit)1173
Start-Up Description1174
Figure 388. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)1174
Figure 389. Start Sequence in Master Mode1175
Clock Generator1176
Figure 390. Audio Sampling Frequency Definition1176
Figure 391. I1176
Table 199. Audio-Frequency Precision Using Standard 8 Mhz HSE1178
I 2 S Master Mode1179
I 2 S Slave Mode1180
I2S Status Flags1182
I2S Error Flags1183
DMA Features1184
I2S Interrupts1184
Table 200. I2S Interrupt Requests1184
SPI and I2S Registers1185
SPI Control Register 1 (Spix_Cr1)1185
SPI Control Register 2 (Spix_Cr2)1187
SPI Status Register (Spix_Sr)1189
SPI Data Register (Spix_Dr)1190
SPI CRC Polynomial Register (Spix_Crcpr)1191
SPI Rx CRC Register (Spix_Rxcrcr)1191
SPI Tx CRC Register (Spix_Txcrcr)1191
Spix_I2S Configuration Register (Spix_I2Scfgr)1192
Spix_I2S Prescaler Register (Spix_I2Spr)1194
SPI/I2S Register Map1195
Table 201. SPI/I2S Register Map and Reset Values1195
FD Controller Area Network (FDCAN)1196
Introduction1196
Table 202. CAN Subsystem I/O Signals1196
Figure 392. CAN Subsystem1197
FDCAN Main Features1198
FDCAN Functional Description1199
Figure 393. FDCAN Block Diagram1199
Bit Timing1200
Operating Modes1201
Figure 394. Bit Timing1201
Table 203. DLC Coding in FDCAN1204
Figure 395. Transceiver Delay Measurement1206
Figure 396. Pin Control in Bus Monitoring Mode1207
Figure 397. Pin Control in Loop Back Mode1209
Message RAM1211
Figure 398. Message RAM Configuration1211
Figure 399. Standard Message ID Filter Path1214
Figure 400. Extended Message ID Filter Path1215
Table 204. Possible Configurations for Frame Transmission1217
FIFO Acknowledge Handling1219
FDCAN Rx FIFO Element1220
Table 205. Rx FIFO Element1220
Table 206. Rx FIFO Element Description1220
FDCAN Tx Buffer Element1222
Table 207. Tx Buffer and FIFO Element1222
Table 208. Tx Buffer Element Description1222
FDCAN Tx Event FIFO Element1224
Table 209. Tx Event FIFO Element1224
Table 210. Tx Event FIFO Element Description1224
FDCAN Standard Message ID Filter Element1225
Table 211. Standard Message ID Filter Element1225
Table 212. Standard Message ID Filter Element Field Description1225
FDCAN Extended Message ID Filter Element1226
Table 213. Extended Message ID Filter Element1226
Table 214. Extended Message ID Filter Element Field Description1226
FDCAN Registers1227
FDCAN Core Release Register (FDCAN_CREL)1227
FDCAN Endian Register (FDCAN_ENDN)1227
FDCAN Data Bit Timing and Prescaler Register (FDCAN_DBTP)1228
FDCAN Test Register (FDCAN_TEST)1229
FDCAN RAM Watchdog Register (FDCAN_RWD)1229
FDCAN CC Control Register (FDCAN_CCCR)1230
FDCAN Nominal Bit Timing and Prescaler Register (FDCAN_NBTP)1232
FDCAN Timestamp Counter Configuration Register (FDCAN_TSCC)1233
FDCAN Timestamp Counter Value Register (FDCAN_TSCV)1234
FDCAN Timeout Counter Configuration Register (FDCAN_TOCC)1235
FDCAN Timeout Counter Value Register (FDCAN_TOCV)1235
FDCAN Error Counter Register (FDCAN_ECR)1236
FDCAN Protocol Status Register (FDCAN_PSR)1236
FDCAN Transmitter Delay Compensation Register (FDCAN_TDCR)1239
FDCAN Interrupt Register (FDCAN_IR)1239
FDCAN Interrupt Enable Register (FDCAN_IE)1242
FDCAN Interrupt Line Select Register (FDCAN_ILS)1244
FDCAN Interrupt Line Enable Register (FDCAN_ILE)1245
FDCAN Global Filter Configuration Register (FDCAN_RXGFC)1245
FDCAN Extended ID and Mask Register (FDCAN_XIDAM)1247
FDCAN High-Priority Message Status Register (FDCAN_HPMS)1247
FDCAN Rx FIFO 0 Status Register (FDCAN_RXF0S)1248
CAN Rx FIFO 0 Acknowledge Register (FDCAN_RXF0A)1249
FDCAN Rx FIFO 1 Status Register (FDCAN_RXF1S)1249
FDCAN Rx FIFO 1 Acknowledge Register (FDCAN_RXF1A)1250
FDCAN Tx Buffer Configuration Register (FDCAN_TXBC)1250
FDCAN Tx Fifo/Queue Status Register (FDCAN_TXFQS)1251
FDCAN Tx Buffer Request Pending Register (FDCAN_TXBRP)1252
FDCAN Tx Buffer Add Request Register (FDCAN_TXBAR)1253
FDCAN Tx Buffer Cancellation Request Register (FDCAN_TXBCR)1253
FDCAN Tx Buffer Transmission Occurred Register (FDCAN_TXBTO)1254
FDCAN Tx Buffer Cancellation Finished Register (FDCAN_TXBCF)1254
FDCAN Tx Buffer Transmission Interrupt Enable Register1255
(Fdcan_Txbtie)1255
FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register1255
(Fdcan_ Txbcie)1255
FDCAN Tx Event FIFO Status Register (FDCAN_TXEFS)1256
FDCAN Tx Event FIFO Acknowledge Register (FDCAN_TXEFA)1256
FDCAN CFG Clock Divider Register (FDCAN_CKDIV)1257
FDCAN Register Map1258
Table 215. FDCAN Register Map and Reset Values1258
Universal Serial Bus Full-Speed Host/Device Interface (USB)1262
Introduction1262
USB Main Features1262
USB Implementation1262
Table 216. Stm32G0X1 USB Implementation1262
USB Functional Description1263
Figure 401. USB Peripheral Block Diagram1263
Description of USB Blocks Used in both Device and Host Modes1265
Description of Host Frame Scheduler (HFS) Specific to Host Mode1266
Programming Considerations for Device and Host Modes1267
Generic USB Device Programming1267
System and Power-On Reset1267
Figure 402. Packet Buffer Areas with Examples of Buffer Description Table Locations1269
Double-Buffered Endpoints and Usage in Device Mode1274
Table 217. Double-Buffering Buffer Flag Definition1275
Table 218. Bulk Double-Buffering Memory Buffers Usage (Device Mode)1275
Double Buffered Channels: Usage in Host Mode1276
Isochronous Transfers in Device Mode1277
Table 219. Bulk Double-Buffering Memory Buffers Usage (Host Mode)1277
Table 220. Isochronous Memory Buffers Usage1278
Isochronous Transfers in Host Mode1279
Suspend/Resume Events1279
Table 221. Isochronous Memory Buffers Usage1279
Table 222. Resume Event Detection1281
Table 223. Resume Event Detection for Host1282
USB and USB SRAM Registers1283
Common Registers1283
Table 224. Reception Status Encoding1300
Table 225. Endpoint/Channel Type Encoding1300
Table 226. Endpoint/Channel Kind Meaning1300
Table 227. Transmission Status Encoding1300
Buffer Descriptor Table1302
Table 228. Definition of Allocated Buffer Memory1303
USB Register Map1306
Table 229. USB Register Map and Reset Values1306
USB Type-C™ / USB Power Delivery Interface (UCPD)1308
Introduction1308
UCPD Main Features1308
UCPD Implementation1308
UCPD Functional Description1309
Table 230. UCPD Implementation1309
UCPD Block Diagram1310
Table 231. UCPD Signals on Pins1310
Figure 403. UCPD Block Diagram1310
UCPD Reset and Clocks1311
Table 232. UCPD Internal Signals1311
Figure 404. Clock Division and Timing Elements1311
Physical Layer Protocol1312
Table 233. 4B5B Symbol Encoding Table1312
Table 234. Ordered Sets1314
Table 235. Validation of Ordered Sets1314
Figure 405. K-Code Transmission1314
Table 236. Data Size1315
Figure 406. Transmit Order for Various Sizes of Data1315
Figure 407. Packet Format1316
Figure 408. Line Format of Hard Reset1316
Figure 409. Line Format of Cable Reset1317
Figure 410. bist Test Data Frame1318
Figure 411. bist Carrier Mode 2 Frame1318
UCPD BMC Transmitter1319
Figure 412. UCPD BMC Transmitter Architecture1319
UCPD BMC Receiver1320
Figure 413. UCPD BMC Receiver Architecture1320
UCPD Type-C Pull-Ups (Rp) and Pull-Downs (Rd)1322
UCPD Type-C Voltage Monitoring and De-Bouncing1322
UCPD Fast Role Swap (FRS) Signaling and Detection1322
UCPD DMA Interface1322
Wakeup from Stop Mode1323
UCPD Programming Sequences1323
Table 237. Coding for ANAMODE, ANASUBMODE and Link with Typec_Vstate_Ccx1323
Table 238. Type-C Sequence (Source: 3A); Cable/Sink Connected (Rd on CC1; Ra on CC2)1325
UCPD Low-Power Modes1327
Table 239. Effect of Low Power Modes on the UCPD1327
UCPD Interrupts1328
Table 240. UCPD Interrupt Requests1328
UCPD Registers1329
UCPD Configuration Register 1 (UCPD_CFGR1)1329
UCPD Configuration Register 2 (UCPD_CFGR2)1331
UCPD Configuration Register 3 (UCPD_CFGR3)1331
UCPD Control Register (UCPD_CR)1332
UCPD Interrupt Mask Register (UCPD_IMR)1335
UCPD Status Register (UCPD_SR)1336
UCPD Interrupt Clear Register (UCPD_ICR)1339
UCPD Tx Ordered Set Type Register (UCPD_TX_ORDSETR)1340
UCPD Tx Payload Size Register (UCPD_TX_PAYSZR)1341
UCPD Tx Data Register (UCPD_TXDR)1341
UCPD Rx Ordered Set Register (UCPD_RX_ORDSETR)1342
UCPD Rx Payload Size Register (UCPD_RX_PAYSZR)1343
UCPD Receive Data Register (UCPD_RXDR)1343
UCPD Rx Ordered Set Extension Register 11344
(Ucpd_Rx_Ordextr1)1344
(Ucpd_Rx_Ordextr2)1344
UCPD Register Map1345
Table 241. UCPD Register Map and Reset Values1345
HDMI-CEC Controller (CEC)1347
Introduction1347
HDMI-CEC Controller Main Features1347
HDMI-CEC Functional Description1348
HDMI-CEC Pin1348
HDMI-CEC Block Diagram1348
Message Description1348
Table 242. HDMI Pin1348
Figure 414. HDMI-CEC Block Diagram1348
Bit Timing1349
Figure 415. Message Structure1349
Figure 416. Blocks1349
Arbitration1350
Figure 417. Bit Timings1350
Figure 418. Signal Free Time1350
SFT Option Bit1351
Figure 419. Arbitration Phase1351
Figure 420. SFT of Three Nominal Bit Periods1351
Error Handling1352
Bit Error1352
Message Error1352
Bit Rising Error (BRE)1352
Figure 421. Error Bit Timing1352
Short Bit Period Error (SBPE)1353
Long Bit Period Error (LBPE)1353
Figure 422. Error Handling1353
Transmission Error Detection (TXERR)1354
Table 243. Error Handling Timing Parameters1354
Table 244. TXERR Timing Parameters1355
Figure 423. TXERR Detection1355
HDMI-CEC Interrupts1356
Table 245. HDMI-CEC Interrupts1356
HDMI-CEC Registers1357
CEC Control Register (CEC_CR)1357
CEC Configuration Register (CEC_CFGR)1358
CEC Tx Data Register (CEC_TXDR)1360
CEC Rx Data Register (CEC_RXDR)1360
CEC Interrupt and Status Register (CEC_ISR)1360
CEC Interrupt Enable Register (CEC_IER)1362
HDMI-CEC Register Map1364
Table 246. HDMI-CEC Register Map and Reset Values1364
Debug Support (DBG)1365
Overview1365
Figure 424. Block Diagram of Stm32G0X1 MCU and Cortex1365
Reference Arm Documentation1366
Pinout and Debug Port Pins1366
SWD Port Pins1366
SW-DP Pin Assignment1366
Table 247. SW Debug Port Pins1366
Internal Pull-Up & Pull-Down on SWD Pins1367
ID Codes and Locking Mechanism1367
SWD Port1367
SWD Protocol Introduction1367
SWD Protocol Sequence1367
SW-DP State Machine (Reset, Idle States, ID Code)1368
Table 248. Packet Request (8-Bits)1368
Table 249. ACK Response (3 Bits)1368
Table 250. DATA Transfer (33 Bits)1368
DP and AP Read/Write Accesses1369
SW-DP Registers1369
Table 251. SW-DP Registers1369
SW-AP Registers1370
Table 252. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]1370
Core Debug1371
BPU (Break Point Unit)1371
Table 253. Core Debug Registers1371
BPU Functionality1372
DWT (Data Watchpoint)1372
DWT Functionality1372
DWT Program Counter Sample Register1372
MCU Debug Component (DBG)1372
Debug Support for Low-Power Modes1372
Debug Support for Timers, Watchdog and I 2 C1373
DBG Registers1373
DBG Device ID Code Register (DBG_IDCODE)1373
Table 254. DEV_ID and REV_ID Field Values1373
DBG Configuration Register (DBG_CR)1374
DBG APB Freeze Register 1 (DBG_APB_FZ1)1374
DBG APB Freeze Register 2 (DBG_APB_FZ2)1376
DBG Register Map1377
Table 255. DBG Register Map and Reset Values1378
Device Electronic Signature1379
Unique Device ID Register (96 Bits)1379
Flash Memory Size Data Register1380
Package Data Register1380
Revision History1382
Table 256. Document Revision History1382

ST STM32G0 1 Series - Figure 294. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0

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