Reset and clock control (RCC) RM0444
190/1390 RM0444 Rev 5
5.4.9 I/O port reset register (RCC_IOPRSTR)
Address: 0x24
Reset value: 0x0000 0000
5.4.10 AHB peripheral reset register (RCC_AHBRSTR)
Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
GPIOF
RST
GPIOE
RST
(1)
GPIOD
RST
GPIOC
RST
GPIOB
RST
GPIOA
RST
rw rw rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFRST: I/O port F reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port F
Bit 4 GPIOERST: I/O port E reset
(1)
This bit is set and cleared by software.
0: no effect
1: Reset I/O port E
Bit 3 GPIODRST: I/O port D reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port D
Bit 2 GPIOCRST: I/O port C reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port C
Bit 1 GPIOBRST: I/O port B reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port B
Bit 0 GPIOARST: I/O port A reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port A