RM0444 Rev 5 171/1390
RM0444 Reset and clock control (RCC)
220
5.2.7 System clock (SYSCLK) selection
One of the following clocks can be selected as system clock (SYSCLK):
• LSI
• LSE
• HSISYS
• HSE
• PLLRCLK
The system clock maximum frequency is 64 MHz. Upon system reset, the HSISYS clock
derived from HSI16 oscillator is selected as system clock. When a clock source is used
directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the Internal
clock source calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and
which clock is currently used as a system clock.
5.2.8 Clock source frequency versus voltage scaling
The following table gives the different clock source frequencies depending on the product
voltage range.
5.2.9 Clock security system (CSS)
Clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock:
• the HSE oscillator is automatically disabled
• a clock failure event is sent to the break input of TIM1, TIM15, TIM16 and TIM17 timers
• CSSI (clock security system interrupt) is generated
The CSSI is linked to the Cortex
®
-M0+ NMI (non-maskable interrupt) exception vector. It
makes the software aware of a HSE clock failure to allow it to perform rescue operations.
Table 35. Clock source frequency
Clock
Maximum clock frequency (MHz)
Range 1 Range 2
HSI16 16 16
HSE 48 16
HSI48 48 N/A
PLLPCLK 122
(1)
1. Maximum VCO frequency is 344 MHz.
40
(2)
2. Maximum VCO frequency is 128 MHz.
PLLQCLK 128
(1)
32
(2)
PLLRCLK 64
(1)
16
(2)
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