Reset and clock control (RCC) RM0444
162/1390 RM0444 Rev 5
Low-power mode security reset
To prevent that critical applications mistakenly enter a low-power mode, three low-power
mode security resets are available. If enabled in option bytes, the resets are generated in
the following conditions:
• Entering Standby mode
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
• Entering Stop mode
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.
• Entering Shutdown mode
This type of reset is enabled by resetting nRST_SHDW bit in user option bytes. In this
case, whenever a Shutdown mode entry sequence is successfully executed, the device
is reset instead of entering Shutdown mode.
For further information on the user option bytes, refer to Section 3.4.1: FLASH option byte
description.
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.
5.1.3 RTC domain reset
The RTC domain has two specific resets.
A RTC domain reset is generated when one of the following events occurs:
• Software reset, triggered by setting the BDRST bit in the RTC domain control register
(RCC_BDCR).
• V
DD
or V
BAT
power on, if both supplies have previously been powered off.
A RTC domain reset only affects the LSE oscillator, the RTC, the backup registers and the
RCC RTC domain control register.
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