ST STM32G0 1 Series

Advanced-control timer (TIM1) RM0444
530/1390 RM0444 Rev 5
Figure 106. Counter timing diagram, internal clock divided by 4
Figure 107. Counter timing diagram, internal clock divided by N
0000 0001
0035
0036
MS31080V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CNT_EN
00
1F
20
MS31081V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)