ST STM32G0 1 Series - Figure 110. Counter Timing Diagram, Internal Clock Divided by 1; Figure 111. Counter Timing Diagram, Internal Clock Divided by 2

RM0444 Rev 5 533/1390
RM0444 Advanced-control timer (TIM1)
624
Figure 110. Counter timing diagram, internal clock divided by 1
Figure 111. Counter timing diagram, internal clock divided by 2
36
34
33
32 31
30 2F
04
03
02 01 00
05
MS31184V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
(cnt_udf)
Update interrupt flag
(UIF)
35
MS31185V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0002
0001
0000
0036
0035
0034
0033