ST STM32G0 1 Series - Table 244. TXERR Timing Parameters; Figure 423. TXERR Detection

RM0444 Rev 5 1355/1390
RM0444 HDMI-CEC controller (CEC)
1364
Figure 423. TXERR detection
Table 244. TXERR timing parameters
Time RXTOL ms Description
T
s
x 0 Bit start event.
T
1
10.3
The earliest time for a low - high transition when
indicating a logical 1.
00.4
T
n1
x0.6
The nominal time for a low - high transition when
indicating a logical 1.
T
2
00.8
The latest time for a low - high transition when
indicating a logical 1.
10.9
T
ns
x 1.05 Nominal sampling time.
T
3
11.2
The earliest time a device is permitted return to a
high impedance state (logical 0).
01.3
T
n0
x1.5
The nominal time a device is permitted return to a
high impedance state (logical 0).
T
4
01.7
The latest time a device is permitted return to a high
impedance state (logical 0).
11.8
T
5
11.85
The earliest time for the start of a following bit.
02.05
T
nf
x 2.4 The nominal data bit period.
T
s
T
1
T
n1
T
2
T
3
T
n0
T
4
T
5
T
nf
T
6
T
ns
Tx arbitration bit-0
Tx data bit-0
Tx arbitration bit-1
Tx data bit-1
Tx acknowledge
MS31012V1
TXERR Checking Window Tolerance margins
Legend:
CEC initiator bit-timing