RM0444 Rev 5 667/1390
RM0444 General-purpose timers (TIM2/TIM3/TIM4)
701
As in the previous example, both counters can be initialized before starting counting.
Figure 209 shows the behavior with the same configuration as in Figure 208 but in trigger
mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
Figure 209. Triggering TIM2 with Enable of TIM3
Starting 2 timers synchronously in response to an external trigger
In this example, we set the enable of TIM3 when its TI1 input rises, and the enable of TIM2
with the enable of TIM3. Refer to Figure 204 for connections. To ensure the counters are
aligned, TIM3 must be configured in Master/Slave mode (slave with respect to TI1, master
with respect to TIM2):
1. Configure TIM3 master mode to send its Enable as trigger output (MMS=001 in the
TIM3_CR2 register).
2. Configure TIM3 slave mode to get the input trigger from TI1 (TS=00100 in the
TIM3_SMCR register).
3. Configure TIM3 in trigger mode (SMS=110 in the TIM3_SMCR register).
4. Configure the TIM3 in Master/Slave mode by writing MSM=1 (TIM3_SMCR register).
5. Configure TIM2 to get the input trigger from TIM3 (TS=00000 in the TIM2_SMCR
register).
6. Configure TIM2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (TIM3), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but an offset can easily be inserted between them by
writing any of the counter registers (TIMx_CNT). One can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on TIM3.
MS33122V1
CK_INT
TIM2-CNT
TIM3-CNT_INIT
Write TIF = 0
TIM3-CEN=CNT_EN
TIM2-TIF
E7
0200 01
E9
75
CD 00 E8 EA
TIM3-CNT
TIM2-CNT_INIT
TIM2
write CNT
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