ST STM32G0 1 Series

Basic timers (TIM6/TIM7) RM0444
706/1390 RM0444 Rev 5
Figure 215. Counter timing diagram, internal clock divided by 2
Figure 216. Counter timing diagram, internal clock divided by 4
MS31079V2
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
0034
0035
0036
0000
0001
0002
0003
0000 0001
0035
0036
MS31080V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
CNT_EN