Reset and clock control (RCC) RM0444
174/1390 RM0444 Rev 5
The multiplexers for MCO and MCO2, respectively, are controlled by the MCOSEL[3:0] and
MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR). Their outputs are
further divided by a factor set through the MCOPRE[2:0] and MCO2PRE[2:0] bitfields of the
Clock configuration register (RCC_CFGR).
Note: The MCO2 output and the associated MCO2SEL[3:0] and MCO2PRE[2:0] bitfields are only
available on the STM32G0B1xx and STM32G0C1xx devices. On the other devices, the
divider ratio is limited to 128 and the clock sources do not include PLLPCLK, PLLQCLK,
HSI48, RTCCLK, and RTC WAKEUP.
LSCO
The LSCO pin allows outputting on of low-speed clocks:
• LSI
• LSE
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit of the
RTC domain control register (RCC_BDCR). The configuration registers of the
corresponding GPIO port must be programmed in alternate function mode.
This function remains available in Stop 0, Stop 1 and Standby modes.
5.2.16 Internal/external clock measurement with TIM14/TIM16/TIM17
It is possible to indirectly measure the frequency of all on-board clock sources with the
TIM14, TIM16 and TIM17 channel 1 input capture, as represented in Figure 12, Figure 13
and Figure 14.
TIM14
By setting the TI1SEL[3:0] field of the TIM14_TISEL register, the clock selected for the input
capture channel1 of TIM14 can be one of:
• GPIO (refer to the alternate function mapping in the device datasheets)
• RTC clock (RTCCLK)
• HSE clock divided by 32
• MCO (MCU clock output)
The last option is controlled by the MCOSEL[3:0] field of the clock configuration register
(RCC_CFGR). All clock sources can be selected for the MCO pin.
Figure 12. Frequency measurement with TIM14 in capture mode
MSv42174V1
TIM 14
TI1
TI1SEL[3:0]
GPIO
HSE
MCO
RTCCLK
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