ST STM32G0 1 Series User Manual

RM0444 Rev 5 191/1390
RM0444 Reset and clock control (RCC)
220
5.4.11 APB peripheral reset register 1 (RCC_APBRSTR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RNG
RST
(1)
Res.
AES
RST
(1)
rw rw
1514131211109 8 76543210
Res. Res. Res.
CRC
RST
Res. Res. Res.
FLASH
RST
Res. Res. Res. Res. Res. Res.
DMA2
RST
(1)
DMA1
RST
rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 RNGRST: Random number generator reset
(1)
Set and cleared by software.
0: No effect
1: Reset RNG
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESRST: AES hardware accelerator reset
(1)
Set and cleared by software.
0: No effect
1: Reset AES
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: No effect
1: Reset CRC
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHRST: Flash memory interface reset
Set and cleared by software.
0: No effect
1: Reset Flash memory interface
This bit can only be set when the Flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 0 DMA2RST: DMA2 and DMAMUX reset
(1)
Set and cleared by software.
0: No effect
1: Reset DMA2 and DMAMUX
Bit 0 DMA1RST: DMA1 and DMAMUX reset
Set and cleared by software.
0: No effect
1: Reset DMA1 and DMAMUX

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English