Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0444
1140/1390 RM0444 Rev 5
35.3 I2S main features
• Half-duplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
• Data format may be 16-bit, 24-bit or 32-bit
• Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
• Programmable clock polarity (steady state)
• Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
• 16-bit register for transmission and reception with one data register for both channel
sides
• Supported I
2
S protocols:
–I
2
S Philips standard
– MSB-justified standard (left-justified)
– LSB-justified standard (right-justified)
– PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
• Data direction is always MSB first
• DMA capability for transmission and reception (16-bit wide)
• Master clock can be output to drive an external audio component. Ratio is fixed at
256 × F
S
(where F
S
is the audio sampling frequency)
35.4 SPI/I2S implementation
The following table describes all the SPI instances and their features embedded in the
devices.
Table 197. STM32G0x1 SPI and SPI/I2S implementation
SPI
Features SPI1 / I2S1 SPI2 / I2S2
(1)
SPI3
(1)
Enhanced NSSP & TI modes Yes Yes Yes
I2S support Yes Yes
(1)
/ No No
Hardware CRC calculation Yes Yes Yes
Data size configuration from 4 to 16-bit from 4 to 16-bit from 4 to 16-bit
Rx/Tx FIFO size 32-bit 32-bit 32-bit
Wakeup capability from Low-power Sleep Yes Yes Yes
1. Applies to STM32G0B1xx and STM32G0C1xx only.
To Next Page
Loading...
Need help?
General
