RM0444 Rev 5 1041/1390
RM0444 Universal synchonous receiver transmitter (USART)
1138
Figure 334. Transmission using DMA
Note: When FIFO management is enabled, the DMA request is triggered by Transmit FIFO not full
(i.e. TXFNF = 1).
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data are loaded from the USART_RDR register to an SRAM area configured using the DMA
peripheral (refer to the corresponding Direct memory access controller section) whenever a
data byte is received. To map a DMA channel for USART reception, use the following
procedure:
1. Write the USART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE (RXFNE in case FIFO mode is enabled) event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from USART_RDR to this memory area after each
RXNE (RXFNE in case FIFO mode is enabled) event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
F2 F3F1
ai17192b
Software
configures DMA
to send 3 data
blocks and
enables USART
The DMA
transfer is
complete
(TCIF=1 in
DMA_ISR)
DMA writes
F1 into
USART_TDR
DMA writes
F2 into
USART_TDR
DMA writes
F3 into
USART_TDR
Software waits until TC=1
Set by hardware
Cleared
by
software
Set by
hardware
TX line
TXE flag
USART_TDR
DMA request
DMA writes
USART_TDR
DMA TCIF flag
(transfer
complete)
TC flag
Frame 1
Frame 2
Frame 3
Idle preamble
Set by hardware
cleared by DMA read
Set by hardware
cleared by DMA read
Set by hardware
Ignored by the DMA because
the transfer is complete
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