RM0444 Rev 5 765/1390
RM0444 General-purpose timers (TIM15/TIM16/TIM17)
830
The output enable signal and output levels during break are depending on several control
bits:
• the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software
and is reset in case of break or break2 event.
• the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in
inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z
mode)
• the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shut-
down level, either active or inactive. The OCx and OCxN outputs cannot be set both to
active level at a given time, whatever the OISx and OISxN values. Refer to Table 127:
Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) on page 795 for more details.
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
function is enabled by setting the BKE bit in the TIMx_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1
APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
A programmable filter (BKF[3:0] bits in the TIMx_BDTR register allows to filter out spurious
events.
The break can be generated from multiple sources which can be individually enabled and
with programmable edge sensitivity, using the TIMx_AF1 register.
The sources for break (BRK) channel are:
• An external source connected to one of the BKIN pin (as per selection done in the
AFIO controller), with polarity selection and optional digital filtering
• An internal source:
– the output from a comparator, with polarity selection and optional digital filtering
– A system break:
- the Cortex
®
-M0+ LOCKUP output
- the PVD output
- the SRAM parity error signal
- a Flash ECC error
- a clock failure event generated by the CSS detector
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