ST STM32G0 1 Series - Page 207

RM0444 Rev 5 207/1390
RM0444 Reset and clock control (RCC)
220
Bit 17 USART2SMEN: USART2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 16 CRSSMEN: CRS clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 15 SPI3SMEN: SPI3 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 14 SPI2SMEN: SPI2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBSMEN: USB clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 12 FDCANSMEN: FDCAN clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 11 WWDGSMEN: WWDG clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 9 USART6SMEN: USART6 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 8 USART5SMEN: USART5 clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 7 LPUART2SMEN: LPUART2 clock enable during Sleep and Stop modes
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 6 Reserved, must be kept at reset value.