RM0444 Rev 5 799/1390
RM0444 General-purpose timers (TIM15/TIM16/TIM17)
830
Bit 27 Reserved, must be kept at reset value.
Bit 26 BKDSRM: Break Disarm
0: Break input BRK is armed
1: Break input BRK is disarmed
This bit is cleared by hardware when no break source is active.
The BKDSRM bit must be set by software to release the bidirectional output control (open-
drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the
fault condition has disappeared.
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bits 25:20 Reserved, must be kept at reset value.
Bits 19:16 BKF[3:0]: Break filter
This bit-field defines the frequency used to sample the BRK input signal and the length of the
digital filter applied to BRK. The digital filter is made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, BRK acts asynchronously
0001: f
SAMPLING
=f
CK_INT
, N=2
0010: f
SAMPLING
=f
CK_INT
, N=4
0011: f
SAMPLING
=f
CK_INT
, N=8
0100: f
SAMPLING
=f
DTS
/2, N=6
0101: f
SAMPLING
=f
DTS
/2, N=8
0110: f
SAMPLING
=f
DTS
/4, N=6
0111: f
SAMPLING
=f
DTS
/4, N=8
1000: f
SAMPLING
=f
DTS
/8, N=6
1001: f
SAMPLING
=f
DTS
/8, N=8
1010: f
SAMPLING
=f
DTS
/16, N=5
1011: f
SAMPLING
=f
DTS
/16, N=6
1100: f
SAMPLING
=f
DTS
/16, N=8
1101: f
SAMPLING
=f
DTS
/32, N=5
1110: f
SAMPLING
=f
DTS
/32, N=6
1111: f
SAMPLING
=f
DTS
/32, N=8
Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in
TIMx_BDTR register).
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details (Section 25.5.9: TIM15 capture/compare
enable register (TIM15_CCER) on page 793).
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
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