Reset and clock control (RCC) RM0444
182/1390 RM0444 Rev 5
Bits 23:20 MCO2PRE[3:0]: Microcontroller clock output 2 prescaler
(1)
This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2
output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Other: reserved
It is highly recommended to set this field before the MCO2 output is enabled.
Bits 19:16 MCO2SEL[3:0]: Microcontroller clock output 2 clock selector
(1)
This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:
0000: no clock, MCO2 output disabled
0001: SYSCLK
0010: HSI48
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: PLLPCLK
1001: PLLQCLK
1010: RTCCLK
1011: RTC WAKEUP
Note: This clock output may have some truncated cycles at startup or during MCO2 clock
source switching.
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 PPRE[2:0]: APB prescaler
This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of
HCLK clock as follows:
0xx: 1
100: 2
101: 4
110: 8
111: 16
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