ST STM32G0 1 Series User Manual

RM0444 Rev 5 1333/1390
RM0444 USB Type-C™ / USB Power Delivery interface (UCPD)
1346
Bit 18 RDCH: Rdch condition drive
The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus
associated with VCONN), by remaining set during the source-only UnattachedWait.SRC
state, to respect the Type-C state. Refer to "USB Type-C ECN for Source VCONN
Discharge". The CCENABLE[1:0] bitfield must be set accordingly, too.
0: No effect
1: Rdch condition drive
Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the
SYSCFG_CFGR1 register.
Bit 17 FRSTX: FRS Tx signaling enable.
Setting the bit enables FRS Tx signaling.
0: No effect
1: Enable
The bit is cleared by hardware after a delay respecting the USB Power Delivery specification
Revision 3.0.
Bit 16 FRSRXEN: FRS event detection enable
Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through
the PHYCCSEL bit. 0: Disable
1: Enable
Clear the bit when the device is attached to an FRS-incapable source/sink.
Bit 15 DBATTEN: Dead battery function enable
The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register.
0: Disable
1: Enable
Dead battery function only operates if the external circuit is appropriately configured.
Bit 14 CC2VCONNEN: VCONN switch enable for CC2
0: Disable
1: Enable
Bit 13 CC1VCONNEN: VCONN switch enable for CC1
0: Disable
1: Enable
Bit 12 Reserved, must be kept at reset value.
Bits 11:10 CCENABLE[1:0]: CC line enable
This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to
ANAMODE and ANASUBMODE[1:0] setting.
0x0: Disable both PHYs
0x1: Enable CC1 PHY
0x2: Enable CC2 PHY
0x3: Enable CC1 and CC2 PHY
A single line PHY can be enabled when, for example, the other line is driven by VCONN via
an external VCONN switch. Enabling both PHYs is the normal usage for sink/source.
Bit 9 ANAMODE: Analog PHY operating mode
The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register.
0: Source
1: Sink
The use of CC1 and CC2 depends on CCENABLE. Refer to Table 237: Coding for
ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield
in conjunction with ANASUBMODE[1:0].

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English