ST STM32G0 1 Series - Page 145

RM0444 Rev 5 145/1390
RM0444 Power control (PWR)
159
Bit 8 PVMENUSB: USB supply voltage monitoring enable
This bit enables the monitoring of the USB supply with respect to 1.2 V threshold.
0: Disable
1: Enable
Bit 7 PVMENDAC: DAC supply voltage monitoring enable
This bit enables the monitoring of the DAC supply with respect to 1.8 V threshold.
0: Disable
1: Enable
Bits 6:4 PVDRT[2:0]: Power voltage detector rising threshold selection.
These bits select the PVD rising threshold:
000: V
PVDR0
(around 2.1 V)
001: V
PVDR1
(around 2.2 V)
010: V
PVDR2
(around 2.5 V)
011: V
PVDR3
(around 2.6 V)
100: V
PVDR4
(around 2.7 V)
101: V
PVDR5
(around 2.9 V)
110: V
PVDR6
(around 3.0 V)
111: PVD_IN pin voltage
Note: If this bitfield is set to 111, the voltage on PVD_IN pin is internally compared with
V
REFINT
for both rising and falling threshold and the PVDFT[2:0] bitfield has no effect.
Note: These bits are write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2
register. The protection can be reset only by a system reset.
Bits 3:1 PVDFT[2:0]: Power voltage detector falling threshold selection.
These bits select the PVD falling threshold:
000: V
PVDF0
(around 2.0 V)
001: V
PVDF1
(around 2.2 V)
010: V
PVDF2
(around 2.4 V)
011: V
PVDF3
(around 2.5 V)
100: V
PVDF4
(around 2.6 V)
101: V
PVDF5
(around 2.8 V)
110: V
PVDF6
(around 2.9 V)
111: Not used
Note: The setting of this bitfield is ignored as long as the bitfield PVDRT[2:0] is set to 111.
Note: These bits are write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2
register. The protection can be reset only by a system reset.
Bit 0 PVDE: Power voltage detector enable
0: Power voltage detector disable.
1: Power voltage detector enable.
Note: This bit is write-protected when the PVD_LOCK bit is set in the SYSCFG_CFGR2
register. The protection can be reset only by a system reset.