Power control (PWR) RM0444
150/1390 RM0444 Rev 5
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 PVMODAC: V
DDA
monitoring output flag
This flag indicates the readiness of the V
DDA
supply voltage (excess of PVM threshold of about
1.8 V).
0: V
DDA
not ready
1: V
DDA
ready
Note: PVMODAC is cleared when PVMDAC is disabled (PVMENDAC = 0). After enabling
PVMDAC, PVMODAC is valid after PVMDAC wakeup time.
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 PVMOUSB: USB supply voltage monitoring output flag
This flag indicates the readiness of the USB supply voltage (excess of 1.2 V).
0: USB supply voltage not ready
1: USB supply voltage ready
Note: PVMOUSB is cleared when PVMUSB is disabled (PVMENUSB = 0). After enabling
PVMUSB, PVMOUSB is valid after the PVMUSB wakeup time.
Bit 11 PVDO: Power voltage detector output
0: V
DD
is above the selected PVD threshold
1: V
DD
is below the selected PVD threshold
Bit 10 VOSF: Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR_CR1 register.
0: The regulator is ready in the selected voltage range
1: The regulator output voltage is changing to the required voltage level
Bit 9 REGLPF: Low-power regulator flag
This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits
the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A
polling on this bit must be done before increasing the product frequency.
This bit is cleared by hardware when the regulator is ready.
0: The regulator is ready in main mode (MR)
1: The regulator is in low-power mode (LPR)
Bit 8 REGLPS: Low-power regulator started
This bit provides the information whether the low-power regulator is ready after a power-on
reset or Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared,
the wakeup from Standby mode time may be increased.
0: The low-power regulator is not ready
1: The low-power regulator is ready
Bit 7 FLASH_RDY: Flash ready flag
This bit is set by hardware to indicate when the Flash memory is ready to be accessed after
wakeup from power-down. To place the Flash memory in power-down, set either
FPD_LPRUN, FPD_LPSLP or FPD_STP bits.
0: Flash memory in power-down
1: Flash memory ready to be accessed
Note: If the system boots from SRAM, the user application must wait till FLASH_RDY bit is
set, prior to jumping to Flash memory.
Bits 6:0 Reserved, must be kept at reset value.
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