Digital-to-analog converter (DAC) RM0444
436/1390 RM0444 Rev 5
Bits 18:16 MODE2[2:0]: DAC channel2 mode
These bits can be written only when the DAC is disabled and not in the calibration mode
(when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write
operation is ignored.
They can be set and cleared by software to select the DAC channel2 mode:
– DAC channel2 in Normal mode
000: DAC channel2 is connected to external pin with Buffer enabled
001: DAC channel2 is connected to external pin and to on chip peripherals with buffer
enabled
010: DAC channel2 is connected to external pin with buffer disabled
011: DAC channel2 is connected to on chip peripherals with Buffer disabled
– DAC channel2 in Sample and hold mode
100: DAC channel2 is connected to external pin with Buffer enabled
101: DAC channel2 is connected to external pin and to on chip peripherals with Buffer
enabled
110: DAC channel2 is connected to external pin and to on chip peripherals with Buffer
disabled
111: DAC channel2 is connected to on chip peripherals with Buffer disabled
Note: This register can be modified only when EN2=0.
Refer to Section 16.3: DAC implementation for the availability of DAC channel2.
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 MODE1[2:0]: DAC channel1 mode
These bits can be written only when the DAC is disabled and not in the calibration mode
(when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write
operation is ignored.
They can be set and cleared by software to select the DAC channel1 mode:
– DAC channel1 in Normal mode
000: DAC channel1 is connected to external pin with Buffer enabled
001: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
010: DAC channel1 is connected to external pin with Buffer disabled
011: DAC channel1 is connected to on chip peripherals with Buffer disabled
– DAC channel1 in sample & hold mode
100: DAC channel1 is connected to external pin with Buffer enabled
101: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
110: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
disabled
111: DAC channel1 is connected to on chip peripherals with Buffer disabled
Note: This register can be modified only when EN1=0.
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