ST STM32G0 1 Series User Manual

List of figures RM0444
46/1390 RM0444 Rev 5
Figure 101. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Figure 102. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 527
Figure 103. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 527
Figure 104. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Figure 105. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Figure 106. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Figure 107. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Figure 108. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 531
Figure 109. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 531
Figure 110. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 111. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Figure 112. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Figure 113. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Figure 114. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 535
Figure 115. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 536
Figure 116. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 117. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 537
Figure 118. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 119. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 538
Figure 120. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 539
Figure 121. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 540
Figure 122. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 123. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 124. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 542
Figure 125. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Figure 126. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 127. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 128. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 129. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 546
Figure 130. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Figure 131. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 547
Figure 132. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Figure 133. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 548
Figure 134. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Figure 135. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Figure 136. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Figure 137. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Figure 138. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 556
Figure 139. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 140. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 558
Figure 141. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 142. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 559
Figure 143. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 560
Figure 144. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
Figure 145. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 564
Figure 146. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 565
Figure 147. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Figure 148. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Figure 149. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 150. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 151. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Figure 152. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English