ST STM32G0 1 Series

List of figures RM0444
48/1390 RM0444 Rev 5
Figure 204. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Figure 205. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . . 664
Figure 206. Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Figure 207. Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 208. Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 209. Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Figure 210. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Figure 211. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Figure 212. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 704
Figure 213. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 704
Figure 214. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Figure 215. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
Figure 216. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
Figure 217. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Figure 218. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Figure 219. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Figure 220. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 709
Figure 221. General-purpose timer block diagram (TIM14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Figure 222. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 718
Figure 223. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 718
Figure 224. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Figure 225. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 226. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 227. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Figure 228. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Figure 229. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Figure 230. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 231. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 723
Figure 232. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 233. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 234. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Figure 235. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Figure 236. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Figure 237. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Figure 238. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 746
Figure 239. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 746
Figure 240. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Figure 241. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Figure 242. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Figure 243. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Figure 244. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Figure 245. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Figure 246. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 752
Figure 247. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 753
Figure 248. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Figure 249. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754