RM0444 Rev 5 57/1390
RM0444 Memory and bus architecture
57
Bus matrix
The bus matrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The bus matrix is composed of
masters (CPU, DMA) and slaves (Flash memory interface, SRAM and AHB-to-APB bridge).
AHB peripherals are connected on system bus through the bus matrix to allow DMA access.
AHB-to-APB bridge (APB)
The AHB-to-APB bridge provides full synchronous connections between the AHB and the
APB bus.
Refer to Section 2.2: Memory organization for the address mapping of the peripherals
connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash
memory). Before using a peripheral its clock in the RCC_AHBENR, RCC_APBENRx or
RCC_IOPENR register must first be enabled.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
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