DocID024597 Rev 3 219/1693
RM0351 Reset and clock control (RCC)
253
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPIRST: Quad SPI memory interface reset
Set and cleared by software.
0: No effect
1: Reset QUADSPI
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller reset
Set and cleared by software.
0: No effect
1: Reset FMC
To Next Page
Loading...
