Direct memory access controller (DMA) RM0351
314/1693 DocID024597 Rev 3
Bits 15:12 C4S[3:0]: DMA channel 4 selection
0000: Channel 4 mapped on DFSDM0
0001: Channel 4 mapped on SPI2_RX
0010: Channel 4 mapped on USART1_TX
0011: Channel 4 mapped on I2C2_TX
0100: Reserved
0101: Channel 4 mapped on TIM7_UP/DAC2
0110: Channel 4 mapped on TIM4_CH2
0111: Channel 4 mapped on TIM1_CH4/TIM1_TRIG/TIM1_COM
others: Reserved
Bits 11:8 C3S[3:0]: DMA channel 3 selection
0000: Channel 3 mapped on ADC3
0001: Channel 3 mapped on SPI1_TX
0010: Channel 3 mapped on USART3_RX
0011: Channel 3 mapped on I2C3_RX
0100: Channel 3 mapped on TIM16_CH1/TIM16_UP
0101: Channel 3 mapped on TIM3_CH4/TIM3_UP
0110: Channel 3 mapped on TIM6_UP/DAC1
0111: Channel 3 mapped on TIM1_CH2
others: Reserved
Bits 7:4 C2S[3:0]: DMA channel 2 selection
0000: Channel 2 mapped on ADC2
0001: Channel 2 mapped on SPI1_RX
0010: Channel 2 mapped on USART3_TX
0011: Channel 2 mapped on I2C3_TX
0100: Channel 2 mapped on TIM2_UP
0101: Channel 2 mapped on TIM3_CH3
0110: Reserved
0111: Channel 2 mapped on TIM1_CH1
others: Reserved
Bits 3:0 C1S[3:0]: DMA channel 1 selection
0000: Channel 1 mapped on ADC1
0001: Reserved
0010: Reserved
0011: Reserved
0100: Channel 1 mapped on TIM2_CH3
0101: Channel 1 mapped on TIM17_CH1/TIM17_UP
0110: Channel 1 mapped on TIM4_CH1
0111: Reserved
others: Reserved
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