Flexible static memory controller (FSMC) RM0351
394/1693 DocID024597 Rev 3
Common memory space timing register 2..4 (FMC_PMEM)
Address offset: Address: 0x88
Reset value: 0xFCFC FCFC
The FMC_PMEM read/write register contains the timing information for NAND Flash
memory bank. This information is used to access either the common memory space of the
NAND Flash for command, address write access and data read/write access.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN IFS ILS IRS
r rwrwrwrwrwrw
Bits 31:7 Reserved, must be kept at reset value
Bit 6 FEMPT: FIFO empty.
Read-only bit that provides the status of the FIFO
0: FIFO not empty
1: FIFO empty
Bit 5 IFEN: Interrupt falling edge detection enable bit
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
Bit 4 ILEN: Interrupt high-level detection enable bit
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
Bit 3 IREN: Interrupt rising edge detection enable bit
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled
Bit 2 IFS: Interrupt falling edge status
The flag is set by hardware and reset by software.
0: No interrupt falling edge occurred
1: Interrupt falling edge occurred
Note: If this bit is written by software to 1 it will be set.
Bit 1 ILS: Interrupt high-level status
The flag is set by hardware and reset by software.
0: No Interrupt high-level occurred
1: Interrupt high-level occurred
Bit 0 IRS: Interrupt rising edge status
The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
Note: If this bit is written by software to 1 it will be set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZx MEMHOLDx
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
MEMWAITx MEMSETx
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
To Next Page
Loading...
Need help?
General
