Analog-to-digital converters (ADC) RM0351
484/1693 DocID024597 Rev 3
Four possible modes are implemented:
• Injected simultaneous mode
• Regular simultaneous mode
• Interleaved mode
• Alternate trigger mode
It is also possible to use these modes combined in the following ways:
• Injected simultaneous mode + Regular simultaneous mode
• Regular simultaneous mode + Alternate trigger mode
• Injected simultaneous mode + Interleaved mode
In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the
bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the
ADCx_CFGR register are shared between the master and slave ADC: the bits in the slave
ADC are always equal to the corresponding bits of the master ADC.
To start a conversion in dual mode, the user must program the bits EXTEN, EXTSEL,
JEXTEN, JEXTSEL of the master ADC only, to configure a software or hardware trigger,
and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave ADC
are don’t care).
In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit
ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the
same time as the master ADC bit.
In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit
JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at
the same time as the master ADC bit.
In dual ADC mode, the converted data of the master and slave ADC can be read in parallel,
by reading the ADC common data register (ADCx_CDR). The status bits can be also read in
parallel by reading the dual-mode status register (ADCx_CSR).
To Next Page
Loading...
Need help?
General
