• FTM0 hardware trigger 0 = SIM_SOPT8[FTM0SYNCBIT] or CMP0 Output or
FTM1 Match (when enabled in the FTM1 External Trigger (EXTTRIG) register)
• FTM0 hardware trigger 1 = PDB channel 1 Trigger Output or FTM2 Match (when
enabled in the FTM2 External Trigger (EXTTRIG) register)
• FTM0 hardware trigger 2 = FTM0_FLT0 pin
• FTM1 hardware trigger 0 = SIM_SOPT8[FTM1SYNCBIT] or CMP0 Output
• FTM1 hardware trigger 1 = CMP1 Output
• FTM1 hardware trigger 2 = FTM1_FLT0 pin
• FTM2 hardware trigger 0 = SIM_SOPT8[FTM2SYNCBIT] or CMP0 Output
• FTM2 hardware trigger 2 = FTM2_FLT0 pin
• FTM3 hardware trigger 0 = SIM_SOPT8[FTM3SYNCBIT] or FTM1 Match (when
enabled in the FTM1 External Trigger (EXTTRIG) register)
• FTM3 hardware trigger 1 = FTM2 Match (when enabled in the FTM2 External
Trigger (EXTTRIG) register)
• FTM3 hardware trigger 2 = FTM3_FLT0 pin
Having FTMxSYNCBIT fields in the same SOPTx register allows the user to
synchronise all FTM timers via their respective TRIG0 input. For the triggers with more
than one additional option, the SIM_SOPT4 register implements control fields for
selecting the option.
3.8.2.7
Input capture options for FTM module instances
The following channel 0 input capture source options are selected via SIM_SOPT4. The
external pin option is selected by default.
• FTM1 channel 0 input capture = FTM1_CH0 pin or CMP0 output or CMP1 output
or USB start of frame pulse
• FTM2 channel 0 input capture = FTM2_CH0 pin or CMP0 output or CMP1 output
• FTM2 channel 1 input capture = FTM2_CH1 pin or exclusive OR of FTM2_CH0,
FTM2_CH1, and FTM1_CH1. See FTM Hall sensor support.
NOTE
When the USB start of frame pulse option is selected as an
FTM channel input capture, disable the USB SOF token
interrupt in the USB Interrupt Enable register
(INTEN[SOFTOKEN]) to avoid USB enumeration conflicts.
Timers
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
114 NXP Semiconductors
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