• In Memory Map / Register Definition added paragraph stating to see chip-specific information re. arbitration.
• In General operation :
• Changed "When a slave bus is being idled by the crossbar,..." to "When a slave bus, other than the flash (if
present), is being idled by the crossbar,...".
• Added paragraph that begins, "If present, the flash slave port parks..."
• General operation : Removed phrase, ", other than the flash (if present),". Removed last paragraph that began with "If
present, the flash slave port..."
• Features :
• Replaced "64-bit data bus" with "Up to single-clock 32-bit transfer".
• Removed bullet beginning with, "Operation at a 1-to-1 clock frequency..." from Features.
• General operation : Removed paragraph beginning with "A master is given control of the targeted slave..." and the
following list, beginning with "A higher priority master has...".
• Fixed-priority operation : Removed the note referring to MGPCR from the "How the Crossbar Switch grants control of a
slave port to a master" table.
• Initialization/application information :
• Changed wording of sentence about arbitration scheme.
A.20 AIPS module changes
Memory map/register definition has been added stating that this module has no registers.
• Edited General operation.
• Corrected misspellings in Memory map/register definition.
A.21 DMAMUX module changes
• Updated the offset address of the registers
• Updated the offset address of registers in the code example given in the section "Enabling and configuring sources"
• Removed the address information of CHCFG1 register (base address + 0x01) and CHCFG8 (base address + 0x08)
from the section "Enabling and configuring sources."
• Updated the section "Features" to show support for 34 peripheral slots.
A.22 eDMA module changes
• Fault reporting and handling : Added note re. cancel transfer request. Added note re. channel priority errors.
• Block parts : Changed "16 bytes of register storage" to "a data buffer" in Data path description.
• Added note to DMA_CR[CLM] description re. restriction on use of continuous link mode.
• In section "Peak transfer rates", added a note stating "All architectures will not meet the assumptions listed above. See
the SRAM configuration section for more information."
• Features : Removed bullet "Error detection and error correction".
• Features : Removed bullet beginning with, "Support to cancel transfers..."
• Memory map/register definition : Edited image in TCD structure for clarity for word at 0008h.
• Made editorial changes in Fault reporting and handling.
Appendix A Release Notes for Revision 4
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1399
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