NXP Semiconductors K22F series User Manual

Bits 15-8 are read-only indicator flags based on the processor’s FPSCR register.
Attempted writes to these bits are ignored. Once set, the flags remain asserted until
software clears the corresponding FPSCR bit.
Address: E008_0000h base + 10h offset = E008_0010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FIDCE
0
FIXCE
FUFCE
FOFCE
FDZCE
FIOCE
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FIDC
0
FIXC
FUFC
FOFC
FDZC
FIOC
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_ISCR field descriptions
Field Description
31
FIDCE
FPU input denormal interrupt enable
0 Disable interrupt
1 Enable interrupt
30–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
FIXCE
FPU inexact interrupt enable
0 Disable interrupt
1 Enable interrupt
27
FUFCE
FPU underflow interrupt enable
0 Disable interrupt
1 Enable interrupt
Table continues on the next page...
Memory map/register descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
402 NXP Semiconductors

NXP Semiconductors K22F series Specifications

General

Brand	NXP Semiconductors
Model	K22F series
Category	Controller
Language	English