x_SACCH field descriptions (continued)
Field Description
0 Associated segment is accessible in supervisor mode only
1 Associated segment is accessible in user or supervisor mode
28.5.4.1.4 Supervisor-only Access Register Low (x_SACCL)
The SACC{H,L} registers provide a bit map for the flash segments to allow supervisor
only or user and supervisor access to the associated segment. SACCH covers segments
63-32 and SACCL supports segments 31-0.
During the reset sequence the SACC register is loaded with a pre-programmed value
from non-volatile space in flash. For more about NVM characteristics, see the functional
description. Any change made to an NVM location takes effect on the next system reset.
The flash basis for the values is signified by x in the reset value.
Address:
0h base + 24h offset = 24h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SA[31:0]
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
Pre-programmed flash valuex = Undefined at reset.•
x_SACCL field descriptions
Field Description
SA[31:0] Supervisor Access for segments 31-0
0 Associated segment is accessible in supervisor mode only
1 Associated segment is accessible in user or supervisor mode
28.5.4.1.5 Configuration Register (x_CR)
The FAC Configuration Register provides basic configuration information including the
flash segment size and an indicator of segment divisions.
The NUMSG and SGSIZE values are fixed for a device. The chip-specific basis for the
values is signified by * in the reset value.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
620 NXP Semiconductors
To Next Page
Loading...
Need help?
General
