Address: 0h base + 1Ch offset = 1Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
XA[31:0]
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
Pre-programmed flash valuex = Undefined at reset.•
x_XACCL field descriptions
Field Description
XA[31:0] Execute-only Access Control for segments 31-0
0 Associated segment is accessible in execute mode only (as an instruction fetch)
1 Associated segment is accessible as data or in execute mode
28.5.4.1.3 Supervisor-only Access Register High (x_SACCH)
The supervisor-only access register is a 64-bit register that is implemented as two 32-bit
registers.
•
High supervisor-only access bits (segments 63-32) are contained in x_SACCH.
•
Low supervisor-only access bits (segments 31-0) are contained in x_SACCL.
The x_SACC{H,L} registers provide a bit map for the flash segments, to allow
supervisor only or user and supervisor access to the associated segment.
During the reset sequence the SACC register is loaded with a pre-programmed value
from non-volatile space in flash. See the functional description for more details on NVM
characteristics. Any change made to an NVM location takes effect on the next system
reset. The flash basis for the values is signified by x in the reset value.
Address:
0h base + 20h offset = 20h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SA[63:32]
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
Pre-programmed flash valuex = Undefined at reset.•
x_SACCH field descriptions
Field Description
SA[63:32] Supervisor Access Control for segments 63-32
Chapter 28 Flash Memory Controller (FMC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 619
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