NXP Semiconductors K22F series - Page 798

The conversion time for a single conversion is calculated by using the Equation 1 on page
796, and the information provided in Table 34-3 through Table 34-7. The table below
lists the variables of Equation 1 on page 796.
Table 34-8. Typical conversion time
Variable Time
SFCAdder 5 ADCK cycles + 5 bus clock cycles
AverageNum 1
BCT 20 ADCK cycles
LSTAdder 0
HSCAdder 0
The resulting conversion time is generated using the parameters listed in the preceding
table. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resulting
conversion time is 3.75 µs.
34.4.4.6.2 Long conversion time configuration
A configuration for long ADC conversion is:
• 16-bit differential mode with the bus clock selected as the input clock source
• The input clock divide-by-8 ratio selected
• Bus frequency of 8 MHz
• Long sample time enabled
• Configured for longest adder
• High-speed conversion disabled
• Average enabled for 32 conversions
The conversion time for this conversion is calculated by using the Equation 1 on page
796, and the information provided in Table 34-3 through Table 34-7. The following table
lists the variables of the Equation 1 on page 796.
Table 34-9. Typical conversion time
Variable Time
SFCAdder 3 ADCK cycles + 5 bus clock cycles
AverageNum 32
BCT 34 ADCK cycles
LSTAdder 20 ADCK cycles
HSCAdder 0
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
798 NXP Semiconductors