NXP Semiconductors LPC1768 - Page 103

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 103 of 841
NXP Semiconductors
UM10360
Chapter 7: LPC176x/5x Pin configuration
P2[12] / EINT2 /
I2STX_WS
51 - I/O P2[12] — General purpose digital input/output pin. 5 V tolerant pad with 5
ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
I
EINT2 — External interrupt 2 input.
I/O
I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the
I
2
S-bus
specification.
P2[13] / EINT3
/
I2STX_SDA
50 - I/O P2[13] — General purpose digital input/output pin. 5 V tolerant pad with 5
ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
I
EINT3 — External interrupt 3 input.
I/O
I2STX_SDA — Transmit data. It is driven by the transmitter and read by
the receiver. Corresponds to the signal SD in the
I
2
S-bus specification.
P3[0] to P3[31] I/O
Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 3 pins depends upon the pin function selected via
the pin connect block. Pins 0 through 24, and 27 through 31 of this port are
not available.
P3[25] / MAT0[0] /
PWM1[2]
27
- I/O P3[25] — General purpose digital input/output pin.
O
MAT0[0] — Match output for Timer 0, channel 0.
O
PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26] / STCLK /
MAT0[1] / PWM1[3]
26
- I/O P3[26] — General purpose digital input/output pin.
I
STCLK — System tick timer clock input.
O
MAT0[1] — Match output for Timer 0, channel 1.
O
PWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31] I/O
Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each
bit. The operation of port 4 pins depends upon the pin function selected via
the pin connect block. Pins 0 through 27, 30, and 31 of this port are not
available.
P4[28] /
RX_MCLK /
MAT2[0] / TXD3
82 65 I/O
P4[28] — General purpose digital input/output pin.
I
RX_MCLK — I
2
S receive master clock.
O
MAT2[0] — Match output for Timer 2, channel 0.
O
TXD3 — Transmitter output for UART3.
P4[29] TX_MCLK /
MAT2[1] / RXD3
85 68 I/O
P4[29] — General purpose digital input/output pin.
I
TX_MCLK — I
2
S transmit master clock.
O
MAT2[1] — Match output for Timer 2, channel 1.
I
RXD3 — Receiver input for UART3.
TDO / SWO 1 1 O
TDO — Test Data out for JTAG interface.
O
SWO — Serial wire trace output.
TDI 22I
TDI — Test Data in for JTAG interface.
TMS / SWDIO 3 3 I
TMS — Test Mode Select for JTAG interface.
I/O
SWDIO — Serial wire debug data input/output.
TRST
44ITRST — Test Reset for JTAG interface.
TCK / SWDCLK 5 5 I
TCK — Test Clock for JTAG interface.
I
SWDCLK — Serial wire clock.
RTCK 100
- I/O RTCK — JTAG interface control signal.
Table 73. Pin description …continued
Symbol LQFP
100
LQFP
80
Type Description