NXP Semiconductors LPC1768 - Page 301

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User manual Rev. 3 — 19 December 2013 301 of 841
NXP Semiconductors
UM10360
Chapter 14: LPC176x/5x UART0/2/3
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Table 270. UART0/2/3 Register Map
Generic Name Description Access Reset
value
[1]
UARTn Register
Name & Address
RBR (DLAB =0) Receiver Buffer Register. Contains the next received
character to be read.
RO NA U0RBR - 0x4000 C000
U2RBR - 0x4009 8000
U3RBR - 0x4009 C000
THR (DLAB =0) Transmit Holding Register. The next character to be
transmitted is written here.
WO NA U0THR - 0x4000 C000
U2THR - 0x4009 8000
U3THR - 0x4009 C000
DLL (DLAB =1) Divisor Latch LSB. Least significant byte of the baud
rate divisor value. The full divisor is used to generate a
baud rate from the fractional rate divider.
R/W 0x01 U0DLL - 0x4000 C000
U2DLL - 0x4009 8000
U3DLL - 0x4009 C000
DLM (DLAB =1) Divisor Latch MSB. Most significant byte of the baud
rate divisor value. The full divisor is used to generate a
baud rate from the fractional rate divider.
R/W 0x00 U0DLM - 0x4000 C004
U2DLM - 0x4009 8004
U3DLM - 0x4009 C004
IER (DLAB =0) Interrupt Enable Register. Contains individual interrupt
enable bits for the 7 potential UART interrupts.
R/W 0x00 U0IER - 0x4000 C004
U2IER - 0x4009 8004
U3IER - 0x4009 C004
IIR Interrupt ID Register. Identifies which interrupt(s) are
pending.
RO 0x01 U0IIR - 0x4000 C008
U2IIR - 0x4009 8008
U3IIR - 0x4009 C008
FCR FIFO Control Register. Controls UART FIFO usage and
modes.
WO 0x00 U0FCR - 0x4000 C008
U2FCR - 0x4009 8008
U3FCR - 0x4009 C008
LCR Line Control Register. Contains controls for frame
formatting and break generation.
R/W 0x00 U0LCR - 0x4000 C00C
U2LCR - 0x4009 800C
U3LCR - 0x4009 C00C
LSR Line Status Register. Contains flags for transmit and
receive status, including line errors.
RO 0x60 U0LSR - 0x4000 C014
U2LSR - 0x4009 8014
U3LSR - 0x4009 C014
SCR Scratch Pad Register. 8-bit temporary storage for
software.
R/W 0x00 U0SCR - 0x4000 C01C
U2SCR - 0x4009 801C
U3SCR - 0x4009 C01C
ACR Auto-baud Control Register. Contains controls for the
auto-baud feature.
R/W 0x00 U0ACR - 0x4000 C020
U2ACR - 0x4009 8020
U3ACR - 0x4009 C020
ICR IrDA Control Register.
Enables and configures the
IrDA mode.
R/W 0x00 U0ICR - 0x4000 C024
U2ICR - 0x4009 8024
U3ICR - 0x4009 C024
FDR Fractional Divider Register. Generates a clock input for
the baud rate divider.
R/W 0x10 U0FDR - 0x4000 C028
U2FDR - 0x4009 8028
U3FDR - 0x4009 C028
TER Transmit Enable Register. Turns off UART transmitter
for use with software flow control.
R/W 0x80 U0TER - 0x4000 C030
U2TER - 0x4009 8030
U3TER - 0x4009 C030