UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 486 of 841
NXP Semiconductors
UM10360
Chapter 20: LPC176x/5x I2S
Fig 101. Typical transmitter master mode, with or without MCLK output
I2STXMODE[3]
I2S_PCLK
÷N
(1 to 64)
8-bit
Fractional
Rate Divider
÷2
XY
I2STX_MCLK
I
2
S
peripheral
block
(transmit)
I2STXBITRATE[5:0]
I2STX_WS
I2STX_SDA
I2STX_CLK
TX_REF TX bit clock
I2STX_RATE[7:0]
I2STX_RATE[15:8]
(Pin OE)
TX_WS ref
Fig 102. Transmitter master mode sharing the receiver reference clock
÷N
(1 to 64)
I2STXBITRATE[5:0]
I2STX_WS
I2STX_SDA
I2STX_CLK
RX_REF TX bit clock
TX_WS ref
I
2
S
peripheral
block
(transmit)
Fig 103. 4-wire transmitter master mode sharing the receiver bit clock and WS
I2STX_WS
I2STX_SDA
I2STX_CLK
RX bit clock
RX_WS ref
I
2
S
peripheral
block
(transmit)
Fig 104. Typical transmitter slave mode
÷N
(1 to 64)
I
2
S
peripheral
block
(transmit)
I2STXBITRATE[5:0]
I2STX_WS
I2STX_SDA
I2STX_CLK
TX_REF TX bit clock
Fig 105. Transmitter slave mode sharing the receiver reference clock
÷N
(1 to 64)
I
2
S
peripheral
block
(transmit)
I2STXBITRATE[5:0]
I2STX_WS
I2STX_SDA
RX_REF TX bit clock
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