NXP Semiconductors LPC1768 - Page 828

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User manual Rev. 3 — 20 December 2013 828 of 841
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NXP Semiconductors
UM10360
Chapter 35: Supplementary information
16.14.2 Section configuration registers . . . . . . . . . . . 378
16.14.3 Standard Frame Individual Start Address register
(SFF_sa - 0x4003 C004) . . . . . . . . . . . . . . . 379
16.14.4 Standard Frame Group Start Address register
(SFF_GRP_sa - 0x4003 C008) . . . . . . . . . . 379
16.14.5 Extended Frame Start Address register (EFF_sa -
0x4003 C00C) . . . . . . . . . . . . . . . . . . . . . . . 379
16.14.6 Extended Frame Group Start Address register
(EFF_GRP_sa - 0x4003 C010) . . . . . . . . . . 380
16.14.7 End of AF Tables register (ENDofTable -
0x4003 C014). . . . . . . . . . . . . . . . . . . . . . . . 380
16.14.8 Status registers. . . . . . . . . . . . . . . . . . . . . . . 380
16.14.9 LUT Error Address register (LUTerrAd -
0x4003 C018). . . . . . . . . . . . . . . . . . . . . . . . 381
16.14.10 LUT Error register (LUTerr - 0x4003 C01C) . 381
16.14.11 Global FullCANInterrupt Enable register (FCANIE
- 0x4003 C020). . . . . . . . . . . . . . . . . . . . . . . 381
16.14.12 FullCAN Interrupt and Capture registers
(FCANIC0 - 0x4003 C024 and FCANIC1 -
0x4003 C028). . . . . . . . . . . . . . . . . . . . . . . . 381
16.15 Configuration and search algorithm . . . . . . 382
16.15.1 Acceptance filter search algorithm . . . . . . . . 382
16.16 FullCAN mode . . . . . . . . . . . . . . . . . . . . . . . . 383
16.16.1 FullCAN message layout . . . . . . . . . . . . . . . 385
16.16.2 FullCAN interrupts . . . . . . . . . . . . . . . . . . . . 387
16.16.2.1 FullCAN message interrupt enable bit . . . . . 387
16.16.2.2 Message lost bit and CAN channel number . 388
16.16.2.3 Setting the interrupt pending bits (IntPnd 63 to
0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
16.16.2.4 Clearing the interrupt pending bits (IntPnd 63 to
0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
16.16.2.5 Setting the message lost bit of a FullCAN
message object (MsgLost 63 to 0) . . . . . . . . 389
16.16.2.6 Clearing the message lost bit of a FullCAN
message object (MsgLost 63 to 0) . . . . . . . . 389
16.16.3 Set and clear mechanism of the FullCAN
interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
16.16.3.1 Scenario 1: Normal case, no message lost . 389
16.16.3.2 Scenario 2: Message lost. . . . . . . . . . . . . . . 390
16.16.3.3 Scenario 3: Message gets overwritten indicated
by Semaphore bits. . . . . . . . . . . . . . . . . . . . 391
16.16.3.4 Scenario 3.1: Message gets overwritten indicated
by Semaphore bits and Message Lost. . . . . 391
16.16.3.5 Scenario 3.2: Message gets overwritten indicated
by Message Lost . . . . . . . . . . . . . . . . . . . . . 392
16.16.3.6 Scenario 4: Clearing Message Lost bit . . . . 393
16.17 Examples of acceptance filter tables and ID
index values. . . . . . . . . . . . . . . . . . . . . . . . . . 394
16.17.1 Example 1: only one section is used . . . . . . 394
16.17.2 Example 2: all sections are used . . . . . . . . . 394
16.17.3 Example 3: more than one but not all sections are
used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
16.17.4 Configuration example 4 . . . . . . . . . . . . . . . 395
16.17.5 Configuration example 5 . . . . . . . . . . . . . . . 395
16.17.6 Configuration example 6 . . . . . . . . . . . . . . . 396
Explicit standard frame format identifier section
(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 397
Group of standard frame format identifier section
(11-bit CAN ID): . . . . . . . . . . . . . . . . . . . . . . . 397
Explicit extended frame format identifier section
(29-bit CAN ID, Figure 72
) . . . . . . . . . . . . . . . 397
Group of extended frame format identifier section
(29-bit CAN ID, Figure 72
) . . . . . . . . . . . . . . . 397
16.17.7 Configuration example 7 . . . . . . . . . . . . . . . 398
FullCAN explicit standard frame format identifier
section (11-bit CAN ID) . . . . . . . . . . . . . . . . . 399
Explicit standard frame format identifier section
(11-bit CAN ID) . . . . . . . . . . . . . . . . . . . . . . . 399
FullCAN message object data section. . . . . . 399
16.17.8 Look-up table programming guidelines . . . . 400
Chapter 17: LPC176x/5x SPI
17.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 402
17.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
17.3 SPI overview. . . . . . . . . . . . . . . . . . . . . . . . . . 402
17.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 403
17.5 SPI data transfers . . . . . . . . . . . . . . . . . . . . . 403
17.6 SPI peripheral details . . . . . . . . . . . . . . . . . . 405
17.6.1 General information . . . . . . . . . . . . . . . . . . . 405
17.6.2 Master operation. . . . . . . . . . . . . . . . . . . . . . 405
17.6.3 Slave operation. . . . . . . . . . . . . . . . . . . . . . . 406
17.6.4 Exception conditions. . . . . . . . . . . . . . . . . . . 406
17.7 Register description . . . . . . . . . . . . . . . . . . . 407
17.7.1 SPI Control Register (S0SPCR - 0x4002
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
17.7.2 SPI Status Register (S0SPSR - 0x4002
0004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
17.7.3 SPI Data Register (S0SPDR - 0x4002 0008) 409
17.7.4 SPI Clock Counter Register (S0SPCCR -
0x4002 000C) . . . . . . . . . . . . . . . . . . . . . . . 409
17.7.5 SPI Test Control Register (SPTCR - 0x4002
0010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
17.7.6 SPI Test Status Register (SPTSR - 0x4002
0014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410