NXP Semiconductors LPC1768 - Page 829

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User manual Rev. 3 — 20 December 2013 829 of 841
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NXP Semiconductors
UM10360
Chapter 35: Supplementary information
17.7.7 SPI Interrupt Register (S0SPINT - 0x4002
001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
17.8 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 412
Chapter 18: LPC176x/5x SSP0/1
18.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 413
18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
18.3 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 413
18.4 Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . 414
18.5 Bus description . . . . . . . . . . . . . . . . . . . . . . . 414
18.5.1 Texas Instruments synchronous serial frame
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
18.5.2 SPI frame format . . . . . . . . . . . . . . . . . . . . . 415
18.5.2.1 Clock Polarity (CPOL) and Phase (CPHA)
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
18.5.2.2 SPI format with CPOL=0,CPHA=0 . . . . . . . . 416
18.5.2.3 SPI format with CPOL=0,CPHA=1 . . . . . . . . 417
18.5.2.4 SPI format with CPOL = 1,CPHA = 0 . . . . . . 417
18.5.2.5 SPI format with CPOL = 1,CPHA = 1 . . . . . . 419
18.5.3 National Semiconductor Microwire frame
format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
18.5.3.1 Setup and hold time requirements on CS with
respect to SK in Microwire mode . . . . . . . . . 421
18.6 Register description . . . . . . . . . . . . . . . . . . . 422
18.6.1 SSPn Control Register 0 (SSP0CR0 -
0x4008 8000, SSP1CR0 - 0x4003 0000). . . 422
18.6.2 SSPn Control Register 1 (SSP0CR1 -
0x4008 8004, SSP1CR1 - 0x4003 0004). . . 423
18.6.3 SSPn Data Register (SSP0DR - 0x4008 8008,
SSP1DR - 0x4003 0008) . . . . . . . . . . . . . . . 424
18.6.4 SSPn Status Register (SSP0SR - 0x4008 800C,
SSP1SR - 0x4003 000C). . . . . . . . . . . . . . . 425
18.6.5 SSPn Clock Prescale Register (SSP0CPSR -
0x4008 8010, SSP1CPSR - 0x4003 0010) . 425
18.6.6 SSPn Interrupt Mask Set/Clear Register
(SSP0IMSC - 0x4008 8014, SSP1IMSC -
0x4003 0014) . . . . . . . . . . . . . . . . . . . . . . . . 425
18.6.7 SSPn Raw Interrupt Status Register (SSP0RIS -
0x4008 8018, SSP1RIS - 0x4003 0018) . . . 426
18.6.8 SSPn Masked Interrupt Status Register
(SSP0MIS - 0x4008 801C, SSP1MIS -
0x4003 001C) . . . . . . . . . . . . . . . . . . . . . . . 426
18.6.9 SSPn Interrupt Clear Register (SSP0ICR -
0x4008 8020, SSP1ICR - 0x4003 0020) . . . 427
18.6.10 SSPn DMA Control Register (SSP0DMACR -
0x4008 8024, SSP1DMACR - 0x4003 0024) 427
Chapter 19: LPC176x/5x I2C0/1/2
19.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 429
19.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
19.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 430
19.4 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 430
19.4.1 I
2
C FAST Mode Plus. . . . . . . . . . . . . . . . . . . 431
19.5 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 431
19.6 I
2
C operating modes . . . . . . . . . . . . . . . . . . . 432
19.6.1 Master Transmitter mode . . . . . . . . . . . . . . . 432
19.6.2 Master Receiver mode . . . . . . . . . . . . . . . . . 433
19.6.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . 434
19.6.4 Slave Transmitter mode . . . . . . . . . . . . . . . . 435
19.7 I
2
C implementation and operation . . . . . . . . 435
19.7.1 Input filters and output stages. . . . . . . . . . . . 435
19.7.2 Address Registers, I2ADR0 to I2ADR3 . . . . 436
19.7.3 Address mask registers, I2MASK0 to
I2MASK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
19.7.4 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 437
19.7.5 Shift register, I2DAT . . . . . . . . . . . . . . . . . . . 437
19.7.6 Arbitration and synchronization logic . . . . . . 437
19.7.7 Serial clock generator. . . . . . . . . . . . . . . . . . 438
19.7.8 Timing and control . . . . . . . . . . . . . . . . . . . . 439
19.7.9 Control register, I2CONSET and I2CONCLR 439
19.7.10 Status decoder and status register. . . . . . . . 439
19.8 Register description . . . . . . . . . . . . . . . . . . . 440
19.8.1 I
2
C Control Set register (I2CONSET: I
2
C0,
I2C0CONSET - 0x4001 C000; I
2
C1,
I2C1CONSET - 0x4005 C000; I
2
C2,
I2C2CONSET - 0x400A 0000). . . . . . . . . . . 441
19.8.2 I
2
C Control Clear register (I2CONCLR: I
2
C0,
I2C0CONCLR - 0x4001 C018; I
2
C1,
I2C1CONCLR - 0x4005 C018; I
2
C2,
I2C2CONCLR - 0x400A 0018). . . . . . . . . . . 443
19.8.3 I
2
C Status register (I2STAT: I
2
C0, I2C0STAT -
0x4001 C004; I
2
C1, I2C1STAT - 0x4005 C004;
I
2
C2, I2C2STAT - 0x400A 0004) . . . . . . . . . 444
19.8.4 I
2
C Data register (I2DAT: I
2
C0, I2C0DAT -
0x4001 C008; I
2
C1, I2C1DAT - 0x4005 C008;
I
2
C2, I2C2DAT - 0x400A 0008) . . . . . . . . . . 444