RM0444 Rev 5 103/1390
RM0444 Embedded Flash memory (FLASH)
118
Bit 8 MISSERR: Fast programming data miss error
In Fast programming mode, 32 double words (256 bytes) must be sent to Flash memory
successively, and the new data must be sent to the logic control before the current data is
fully programmed. MISSERR is set by hardware when the new data is not present in time.
Cleared by writing 1.
Bit 7 PGSERR: Programming sequence error
Set by hardware when a write access to the Flash memory is performed by the code while
PG or FSTPG have not been set previously. Set also by hardware when PROGERR,
SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous
programming error.
Cleared by writing 1.
Bit 6 SIZERR: Size error
Set by hardware when the size of the access is a byte or half-word during a program or a fast
program sequence. Only double word programming is allowed (consequently: word access).
Cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same double word
(64-bit) Flash memory in case of standard programming, or if there is a change of page
during fast programming.
Cleared by writing 1.
Bit 4 WRPERR: Write protection error
Set by hardware when an address to be erased/programmed belongs to a write-protected
part (by WRP, PCROP or RDP Level 1) of the Flash memory.
Cleared by writing 1.
Bit 3 PROGERR: Programming error
Set by hardware when a double-word address to be programmed contains a value different
from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'.
Cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error
Set by hardware when a Flash memory operation (program / erase) completes
unsuccessfully.
This bit is set only if error interrupts are enabled (ERRIE=1).
Cleared by writing ‘1’.
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operation (programming / erase) has
been completed successfully.
This bit is set only if the end of operation interrupts are enabled (EOPIE=1).
Cleared by writing 1.
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