RM0444 Rev 5 1305/1390
RM0444 Universal serial bus full-speed host/device interface (USB)
1307
Channel/endpoint transmit buffer descriptor n [alternate]
(USB_CHEP_RXTXBD_n)
Address offset: n*8 + 4
This register description applies when corresponding CHEPnR register programs use of
double buffering and activates transmit buffers (otherwise refer to previous register
description).
Bits 25:16 COUNTn_RX[9:0]: Reception byte count
These bits contain the number of bytes received by the endpoint/channel associated with the
USB_CHEPnR register during the last OUT/SETUP transaction addressed to it.
Bits 15:0 ADDRn_RX[15:0]: Reception buffer address
These bits point to the starting address of the packet buffer, which contains the data received
by the endpoint/channel associated with the USB_CHEPnR register at the next OUT/SETUP
token addressed to it. Bits 1 and 0 must always be written as “00” since packet memory is
word wide and all packet buffers must be word aligned.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. COUNTn_TX[9:0]
rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
ADDRn_TX[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:26 Reserved, must be kept at reset value.
Bits 25:16 COUNTn_TX[9:0]: Transmission byte count
These bits contain the number of bytes to be transmitted by the endpoint/channel associated
with the USB_CHEPnR register at the next IN token addressed to it.
Bits 15:0 ADDRn_TX[15:0]: Transmission buffer address
These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint/channel associated with the USB_CHEPnR register at the next IN token
addressed to it. Bits 1 and 0 must always be written as “00” since packet memory is word
wide and all packet buffers must be word aligned.
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