RM0444 Rev 5 1375/1390
RM0444 Debug support (DBG)
1378
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address offset: 0x08
Power on reset (POR): 0x0000 0000 (not reset by system reset)
Only 32-bit access are supported.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
DBG_LPTIM2_STOP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DBG_I2C2_SMBUS_TIMEOUT
(1)
DBG_I2C1_SMBUS_TIMEOUT
Res.
Res.
Res.
Res.
Res.
rw rw rw rw
1514131211109876543210
Res.
Res.
Res.
DBG_IWDG_STOP
DBG_WWDG_STOP
DBG_RTC_STOP
Res.
Res.
Res.
Res.
DBG_TIM7_STOP
DBG_TIM6_STOP
Res.
DBG_TIM4_STOP
(2)
DBG_TIM3_STOP
DBG_TIM2_STOP
rw rw rw rw rw rw rw rw
1. Only significant on devices integrating I2C2, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
2. Only significant on devices integrating TIM4, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bit 31 DBG_LPTIM1_STOP: Clocking of LPTIMER1 counter when the core is halted
This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:
0: Enable
1: Disable
Bit 30 DBG_LPTIM2_STOP: Clocking of LPTIMER2 counter when the core is halted
This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:
0: Enable
1: Disable
Bits 29:23 Reserved, must be kept at reset value.
Bit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
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