ST STM32G0 1 Series - Page 1384

Revision history RM0444
1384/1390 RM0444 Rev 5
19-May-2020
3
cont’d
– Section 33.4: USART implementation updated - tables reorganized
– Section 34.3: LPUART implementation updated - tables reorganized
– Section 38: USB Type-C™ / USB Power Delivery interface (UCPD): general
update
– former DAC trigger connection table renamed as Table 82: DAC
interconnection and moved to Section 16.4.2: DAC pins and internal signals
– Table 254: DEV_ID and REV_ID field values
– Section 40.10.2: DBG configuration register (DBG_CR)
6-Oct-2020 4 Updated Section 3.4.2: FLASH option byte programming.
20-Nov-2020 5
Extension of the document scope to cover STM32G051xx, STM32G061xx,
STM32G0B1xx, and STM32G0C1xx devices, with corresponding addition or
update of:
– Section 1.1: General information
– Section 1.4: Availability of peripherals
– Section 2: Memory and bus architecture
– Section 3: Embedded Flash memory (FLASH)
– Section 4: Power control (PWR)
– Section 5: Reset and clock control (RCC)
– Section 8: System configuration controller (SYSCFG)
– Section 9: Interconnect matrix
– Section 10: Direct memory access controller (DMA)
– Section 11: DMA request multiplexer (DMAMUX)
– Section 12: Nested vectored interrupt controller (NVIC)
– Section 13: Extended interrupt and event controller (EXTI)
– Section 15: Analog-to-digital converter (ADC)
– Section 18: Comparator (COMP)
– Section 20: AES hardware accelerator (AES)
– Section 21: Advanced-control timer (TIM1)
– Section 22: General-purpose timers (TIM2/TIM3/TIM4)
– Section 24: General-purpose timers (TIM14)
– Section 25: General-purpose timers (TIM15/TIM16/TIM17)
– Section 26: Low-power timer (LPTIM)
– Section 32: Inter-integrated circuit (I2C) interface
– Section 33: Universal synchonous receiver transmitter (USART)
– Section 34: Low-power universal asynchronous receiver transmitter
(LPUART)
– Table 31Section 31: Tamper and backup registers (TAMP)
– Section 35: Serial peripheral interface / integrated interchip sound (SPI/I2S)
– Section 37: Universal serial bus full-speed host/device interface (USB)
– Section 36: FD controller area network (FDCAN)
– Section 41: Device electronic signature
Table 256. Document revision history (continued)
Date Revision Changes