ST STM32G0 1 Series - Page 1383

RM0444 Rev 5 1383/1390
RM0444 Revision history
1384
19-May-2020 3
– Empty check section
– Section 3.3.8: FLASH Main memory programming sequences
– User and read protection option bytes section
– Option byte loading section
– Table 19: Access status versus protection level and execution modes
– Section 3.5.4: Securable memory area
– Section 3.7.1: FLASH access control register (FLASH_ACR)
– Section 3.7.8: FLASH option register (FLASH_OPTR) (BORR_LEV[1:0]
swapped with BORF_LEV[1:0]
– Section 3.7.9: FLASH PCROP area A start address register
(FLASH_PCROP1ASR) to Section 3.7.14: FLASH PCROP area B end
address register (FLASH_PCROP1BER): reset values
– Section 7.3: GPIO functional description: introductory information modified
– Section 7.3.15: USB PD / Dead battery support: description filled
– Table 48: Programmable data width and endian behavior (when
PINC = MINC = 1): NDT in the first row corrected from 8 to 4
– Table 52: DMAMUX: assignment of multiplexer inputs to resources:
TIM16/17_TRG_COM corrected to TIM16/17_COM
– Section 15.2: ADC main features: V
TS
corrected to V
SENSE
– Section 15.3.1: ADC pins and internal signals: tables and their organization
(External triggers table brought to this section)
– Table 71: Latency between trigger and start of conversion: latency values
– Section : Calculating the actual V
REF+
voltage using the internal reference
voltage - corrected from V
DDA
to V
REF+
– Section 20: AES hardware accelerator (AES): general update
– Section 21: Advanced-control timer (TIM1): general update
– Figure 187: Capture/Compare channel 1 main circuit and Figure 188: Output
stage of Capture/Compare channel (channel 1) updated
– Figure 205: Master/slave connection example with 1 channel only timers
added
– Table 120: Output control bit for standard OCx channels updated
– Section 22.4.29: TIM3 timer input selection register (TIM3_TISEL): removed
TI4SEL[3:0] and TI3SEL[3:0]
– Figure 221: General-purpose timer block diagram (TIM14): updated
– Figure 232: Capture/compare channel 1 main circuit and Figure 233: Output
stage of capture/compare channel (channel 1) updated
– Section 24.3.11: Using timer output as trigger for other timers (TIM14) added
– Figure 251: Capture/compare channel 1 main circuit updated
– Section 25.4.23: Using timer output as trigger for other timers
(TIM16/TIM17) added
–Former Section 28.3.4 Advanced watchdog interrupt feature moved to
Section 29.4: WWDG interrupts
– Section 32.4.3: I2C pins and internal signals added
– Section 32.7.3: I2C own address 1 register (I2C_OAR1) and Section 32.7.8:
I2C interrupt clear register (I2C_ICR) updated
Table 256. Document revision history (continued)
Date Revision Changes