ST STM32G0 1 Series - Page 164

Reset and clock control (RCC) RM0444
164/1390 RM0444 Rev 5
The peripherals are clocked with the clocks from the bus they are attached to (HCLK for
AHB, PCLK for APB) except:
• TIMx, with these clock sources to select from:
– TIMPCLK (selectable for all timers) running at PCLK frequency if the APB
prescaler division factor is set to 1, or at twice the PCLK frequency otherwise
– PLLQCLK selectable for high-speed TIM1 and TIM15 timers
• LPTIMx, with these clock sources to select from:
–LSI
–LSE
–HSI16
– PCLK (APB clock)
– LPTIMx_IN selected from LPTIMx_INx pins
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• UCPD, always clocked with HSI16
• ADC, with these clock sources to select from:
– SYSCLK (system clock)
–HSI16
–PLLPCLK
• USARTx / LPUARTx, with these clock sources to select from:
– SYSCLK (system clock)
–HSI16
–LSE
– PCLK (APB clock)
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
• I2Cx, with these clock sources to select from:
– SYSCLK (system clock)
–HSI16
– PCLK (APB clock)
The wakeup from Stop mode is supported only when the clock is HSI16.
• I2Sx, with these clock sources to select from:
– SYSCLK (system clock)
–HSI16
–PLLPCLK
– I2S_CKIN pin
• RNG, with these clock sources to select from:
– SYSCLK (system clock)
– HSI16 clock divided by 8
– PLLQCLK
The RNG clock can additionally be divided by 2, 4 or 8, using a dedicated prescaler.