RM0444 Rev 5 185/1390
RM0444 Reset and clock control (RCC)
220
Bits 21:17 PLLP[4:0]: PLL VCO division factor P for PLLPCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor P as follows:
00000: Reserved
00001: 2
...
11111: 32
The bitfield can be written only when the PLL is disabled.
Caution: The software must set this bitfield so as not to exceed 122 MHz on this clock.
Bit 16 PLLPEN: PLLPCLK clock output enable
This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL:
0: Disable
1: Enable
Disabling the PLLPCLK clock output, when not used, allows saving power.
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLN[6:0]: PLL frequency multiplication factor N
This bit is controlled by software to set the division factor of the f
VCO
feedback divider (that
determines the PLL multiplication ratio) as follows:
0000000: Invalid
0000001: Reserved
...
0000111: Reserved
0001000: 8
0001001: 9
...
1010101: 85
1010110: 86
1010111: Reserved
...
1111111: Reserved
The bitfield can be written only when the PLL is disabled.
Caution: The software must set these bits so that the VCO output frequency is between 64
and 344 MHz.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLLM: Division factor M of the PLL input clock divider
This bit is controlled by software to divide the PLL input clock before the actual phase-locked
loop, as follows:
000: 1
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
Caution: The software must set these bits so that the PLL input frequency after the /M divider
is between 2.66 and 16 MHz.
Bits 3:2 Reserved, must be kept at reset value.
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